9/4/2001 ECE 551 Fall ECE Digital System Design & Synthesis Lecture 1 - Introduction  Overview oCourse Introduction oOverview of Contemporary Digital Design  Layout Lite  Application Specific Integrated Circuit (ASIC) Technologies  IC Costs  ASIC Design Flows The Role of HDLs and Synthesis  Summary

9/4/2001 ECE 551 Fall Course Introduction  Purpose: oTo provide knowledge and experience in performing contemporary logic design based on 1) hardware description languages (HDLs), 2) HDL simulation, 3) automated logic synthesis and 4) timing analysis with consideration for a) pragmatic design and test issues, b) chip layout issues, and c) design reuse in the context of the ASIC (Application Specific Integrated Circuit) and SOC (System-On-a-Chip) technologies.  Conduct and Outline ohttp:// duct_551.htmlhttp:// duct_551.html

9/4/2001 ECE 551 Fall Layout Lite  IC are produced from masks that correspond to geometric layouts produced by the designer or automatically.  In CMOS, a typical IC cross-section: Substrate Oxide Transistor Metal 3 Metal 2 Metal 1 Polysilicon Diffusion Channel

9/4/2001 ECE 551 Fall Layout Lite (continued)  The layout corresponding to the cross-section: oThe transistor is outlined in broad yellow lines. oEverything else is interconnect. Channel Transistor

9/4/2001 ECE 551 Fall IC Implementation Technologies  Implementation technologies are distinguished by: oThe levels of the layout 1) transistors and 2) interconnect that are:  Common to distinct IC designs (L1)  Different for distinct IC designs (L2) oThe use of predesigned layout cells  Predesigned cells are used (P1)  Predesigned cells are not used (P2) oMechanism used for instantiating distinct IC designs:  Metallization (M)  Fuses or Antifuses (F)  Stored Charge (C)  Static Storage (R)

9/4/2001 ECE 551 Fall IC Implementation Technologies (continued) STANDARD IC FULL CUSTOM SEMI - CUSTOM FIELD PROGRAMMABLE STANDARD CELL GATE ARRAY, SEA OF GATES ASICFPGAPLD

9/4/2001 ECE 551 Fall IC Implementation Technologies (continued)  Technologies in terms of Distinguishing Features: oFull Custom – P2, M  Transistors – L2, Interconnects – L2 oStandard Cell – P1, M  Transistors – L2, Interconnects – L2 oGate Array, Sea of Gates – P1, M  Transistors – L1, Interconnects – L2 oFPGA – P1, F or R  Transistors – L1, Interconnects – L1 oPLD – P1, F or C  Transistors – L1, Interconnects – L1

9/4/2001 ECE 551 Fall IC Implementation Technologies (continued)  Technologies in terms of shared fabrication steps (can be used for common transistors/interconnects): oFull Custom and Standard Cells – all layers are custom fabricated oGate Arrays and Sea of Gates – only interconnect (metallization) layers custom fabricated oFPGAs and PLDs – nothing is custom fabricated  Consequences due to economy-of-scale: oFab costs reduced for Gate Arrays and Sea of Gates oFab costs further reduced for FPGAs and PLDs

9/4/2001 ECE 551 Fall IC Implementation Technologies (continued)  Technologies in terms of layout styles: Adjustable Spacing Megacells Standard Cell Gate Array - Channeled … … Fixed Spacing Base Cell

9/4/2001 ECE 551 Fall IC Implementation Technologies (continued)  Technologies in terms of layout styles: … Base Cell Gate Array - Channel-less (Sea of Gates) Gate Array - Structured … … Fixed Embedded Block

9/4/2001 ECE 551 Fall IC Costs  An example: 10,000 gate circuit [1] oFixed costs  Standard Cell - $146,000  Gate Array - $86,000  FPGA - $21,800 oVariable costs  Standard Cell - $8 per IC  Gate Array - $10 per IC  FPGA - $39 per IC

9/4/2001 ECE 551 Fall IC Costs (continued)  An example: 10,000 gate circuit

9/4/2001 ECE 551 Fall IC Costs (continued)  Why isn’t FPGA cheaper per unit due to economy-of-scale? oThe chip area required by each of the successive technologies from Full Custom to FPGAs increases for a fixed-sized design. oThe larger the chip area, the poorer the yield of working chips during fabrication oAlso, due to increased sales, FPGA prices have declined since the mid-90’s much faster than the other technologies.

9/4/2001 ECE 551 Fall Draw Datapath Schematics * Traditional ASIC Design Flow Write Specifications Define System Architecture Partition - Data- path &Control Define State Diag/Tables Draw Control Schematics * Integrate Design* Do Physical Design* Implement* * Steps followed by validation and refinement

9/4/2001 ECE 551 Fall Traditional Flow Problems  Schematic Diagrams oLimited descriptive power  State Diagrams and Algorithmic State Machines oLimited portability oLimited complexity oDifficult to describe parallelism oLimited complexity  Tedious and/or Repetitive Detail

9/4/2001 ECE 551 Fall How about HDLs Instead of Diagrams?  HDLs oHighly portable (text) oDescribes multiple levels of abstraction oRepresents parallelism oProvides many descriptive styles  Structural  Register Transfer Level (RTL)  Behavioral oServe as input for synthesis

9/4/2001 ECE 551 Fall How about Synthesis instead of Manual Design?  Increased design efficiency  Reduces verification/validation problem  Ability to explore more of overall design space  Are there disadvantages?  Potential for better optimization

9/4/2001 ECE 551 Fall Refine to RTL (HDL)* Physical Design* Synthesis Design Flow Write Specifications Define Architec- ture (HDL)* Implement* * Steps followed by validation and refinement Partition Arch- itecture Synthesize RTL*

9/4/2001 ECE 551 Fall Synthesize RTL* Contemporary Design Flow Write Specifications Define Architec- ture (HDL)* Implement* * Steps followed by validation and refinement Partition Arch- itecture Refine to RTL* Preliminary Physical Design Select IP Cores Physical Design*

9/4/2001 ECE 551 Fall Summary oCourse Conduct – Be familiar with it oApplication Specific Integrated Circuit (ASIC) Technologies – provides a basis for understanding what we are designing oIC Costs – Gives a basis for technology selection oASIC Design Flows  The role of HDLs and synthesis  Provides a structure for what we are to learn

9/4/2001 ECE 551 Fall References 1) Smith, Michael J. S., Application-Specific Integrated Circuits, Addison-Wesley, 1997.