V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100 nm frontier V. Re a,c, L. Gaioni b,c, M. Manghisoni a,c, L. Ratti b,c, G. Traversi a,c c INFN Sezione di Pavia a Università di Bergamo Dipartimento di Ingegneria Industriale b Università di Pavia Dipartimento di Elettronica

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Industrial microelectronic technologies are today well beyond the 130 nm CMOS generation that is currently the focus of IC designers for LHC upgrades and other applications Sub-100 nm CMOS is appealing for the design of very compact front-end systems with advanced integrated functionalities, such as required by pixel sensors with low pitch:  MAPS  Hybrid pixels (high resistivity sensors connected to CMOS readout chips) Motivation Digital performances (speed, density, power dissipation) are driving the evolution of CMOS technologies. What about analog performance?

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Nanoscale CMOS New materials and processing techniques are used to match specifications of sub- 100 nm CMOS nodes. The gate dielectric has evolved to comply with scaling rules while avoiding too large tunneling currents. New physical device parameters may impact on functional properties such as noise and radiation hardness Focus of this talk: provide information for the design of low-noise, rad-hard analog blocks Gate leakage current and 1/f noise are appropriate tools to investigate the impact of nanoscale CMOS processing on the quality of the gate dielectric. Source:Intel

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Investigated technologies and devices 90 nm CMOS transistors by foundry A and B (standard interdigitated layout) Technology features: –Supply voltage V DD = 1.2 V V DD = 1 V –Electrical oxide thickness t OX = 2.4 nm t OX = 2 nm –Gate capacitanceC OX = 15 fF/μm 2 C OX = 18 fF/μm 2 Preview of data for 65 nm CMOS LP (Low Power) transistors by foundry B Comparison with previous generations, back to 350 nm 130 nm CMOS transistors by foundry A (standard interdigitated layout) and C (enclosed layout) 130 nm 90 nm These processes continue to use poly gates; a certain level of nitridation is used in the the SiO 2 gate dielectric (no high-k)

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, N+N+ N+N+ Nanoscale MOSFETs Thin gate oxide (~ 1-2 nm) for core devices, gate tunneling current kept under control by gate processing (e.g. SiON in the dielectric, new gate electrode materials). Thick Shallow Trench Isolation Oxide (~ 300 nm); radiation-induced charge- buildup may turn on noisy lateral parasitic transistors G S D P-well STI P-substrate Doping profile along STI sidewall is critical; doping increases with CMOS scaling Increasing sidewall doping makes a device less sensitive to radiation (more difficult to form parasitic leakage paths) Strained silicon to improve device performance

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Operating region Under reasonable power dissipation constraints, the preamplifier input device operates in the weak inversion region μ carrier mobility C OX specific gate oxide capacitance V T thermal voltage n proportional to I D (V GS ) subthreshold characteristic Operating point for W/L =400/0.2 (strips), I D = 100 A W/L =40/0.2 (pixels), I D =10 A

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Gate current Charge carriers have a nonzero probability (larger for electrons with respect to holes) of directly tunneling through a silicon dioxide layer with a physical thickness < 2 nm (100-nm scale CMOS). Reduction of physical oxide thickness of a few Å may give several orders of magnitude increase in the gate current. Gate dielectric nitridation increases the dielectric constant, allowing for films with a larger physical thickness as compared with SiO 2 (C OX =  OX /t OX ). This mitigates the gate leakage current; however, its value can sizably change in devices from different foundries.

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Gate current density in different CMOS generations and foundries We made tests on 65 nm LP (Low Power) transistors (V DD = 1.2 V). These devices were optimized for a reduced leakage (larger equivalent oxide thickness, different level of nitridation with respect to other flavours, different silicon stress ). 90 nm CMOS transistors by foundries A and B have very different gate current levels (2-3 orders of magnitude) The gate current of 65 nm LP transistors is of the same order as in the 90 nm node (same foundry)

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, /f noise White noise Parallel noise Effect of gate current on noise performance Even in the worst case (90 nm process from Foundry A) series white noise remains dominant at t P < 100 ns. For fast front-end electronics systems, gate leakage current should not have a sizable impact on the noise. M. Manghisoni, “Gate Current Noise in Ultrathin Oxide MOSFETs and Its Impact on the Performance of Analog Front-End Circuits”, IEEE TNS, Vol. 55 no. 4 pp Aug. 2008

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, /f noise: gate stack fabrication process The process recipe for the gate stack (gate electrode and dielectric) may affect the density of oxide traps and their interaction with charge carriers in the channel, impacting on the 1/f noise spectral density. Gate dielectric nitridation was found to degrade 1/f noise because of the higher interface state density. For a physical oxide thickness < 2 nm (same order of the tunnelling distance) the traps at the interface between the gate dielectric and the gate electrode (fully silicided poly gates) can play a major role. 1/f noise may be affected by mechanical stress in the silicon channel (enhanced carrier mobility and drive current).

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, /f noise in NMOS: CMOS generations from 250 nm to 65 nm 1/f noise has approximately the same magnitude (for a same WLC OX ) across different CMOS generations. White noise has also very similar properties (weak/moderate inversion). k f 1/f noise parameter α f 1/f noise slope-related coefficient k B Boltzmann’s constant T absolute temperature α w excess noise coefficient γ channel thermal noise coefficient In weak inversion: 1/f noise Channel thermal noise

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, /f noise from 350 nm to 65 nm CMOS The 1/f noise parameter K f does not show dramatic variations across different CMOS generations and foundries. k f 1/f noise parameter α f 1/f noise slope-related coefficient ( 0.85 in NMOS,  1 – 1.1 in PMOS )

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, /f noise in PMOS: CMOS generations from 250 nm to 90 nm 1/f noise appears to increase (for a same WLC OX ) with CMOS scaling

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, /f noise: NMOS vs PMOS In deep submicron processes, it was expected that the PMOS would behave as a surface channel device, rather than a buried channel one as in older CMOS generations. With an inversion layer closer to the oxide interface, 1/f noise is expected to increase. Ultimately, PMOSFETs should feature the same 1/f noise properties as NMOSFETs. However, this was not observed in CMOS generations down to 130 nm and 90 nm. In bulk CMOS, the fact that PMOSFETs feature a smaller 1/f noise with respect to equally sized NMOSFETs was generally related to buried channel conduction. A possible interpretation can be related to the different interaction of electrons (NMOS) and holes (PMOS) with traps in the gate dielectric (different barrier energies experienced by holes and electrons across the Si/SiO 2 interface).

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, We previously found that NMOS and PMOS have the same 1/f noise only in one case, that is, in fully-depleted 180 nm CMOS SOI transistors. A possible explanation was that in a very thin silicon film (40 nm) conduction takes place very close to the Si-SiO 2 interface. NMOS and PMOS in an FD-SOI technology

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, /f noise: NMOS vs PMOS Difference tends to decrease with newer CMOS generations.

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, nm LP process: 1/f noise In the 65 nm LP process by Foundry B, NMOS and PMOS have similar 1/f noise (especially longer transistors). This could be explained by a “surface channel” behavior for both devices, and/or by the fact that the gate dielectric nitridation decreases the barrier energy experienced by holes across the silicon-dielectric interface. This would make it easier for the PMOS channel to exchange charges with oxide traps.

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Ionizing radiation effects in sub-100 nm CMOS Radiation induced positive charge is removed from thin gate oxides by tunneling (which also prevents the formation of interface states) Isolation oxides remain thick (order of 100 nm) also in nanoscale CMOS, and they are radiation soft. With scaling, the effect of positive charge buildup in STI oxides appears to be mitigated by the higher doping of the silicon bulk. However, the radiation-induced noise degradation may be sizable. This is associated to noisy lateral parasitic transistors. The use of enclosed devices for low-noise functions will help.

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, L STI mfmf 12 In NMOSFETs edge effects due to radiation-induced positive charge in the STI oxide generate sidewall leakage paths. Gate Drain Source n+n+ n+ poly STI Main transistor finger Source Drain Gate Lateral parasitic devices NMOSFETs and lateral leakage NMOS finger Multifinger NMOS Shaneyfelt et al, “Challenges in Hardening Technologies using Shallow-Trench Isolation” IEEE TNS, Dec Lateral transistors have the same gate length as the main MOSFET

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Radiation effects on noise: 90 nm NMOS In 90 nm open layout NMOSFETs, at 10 Mrad total dose the main radiation effect is a 1/f noise increase at low current density, due to the contribution of lateral parasitic devices. No increase in the white noise region is detected.

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Radiation effects: 90 nm vs 130 nm NMOS The noise increase seems to saturate at a total dose of several Mrad (smaller in 130 nm devices). This is in agreement with the behavior of the lateral leakage current in irradiated devices (saturation effect in positive charge build- up in the STI oxide, along with a compensating effect from interface states)

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Radiation effects on noise: 130 nm enclosed NMOS In 130 nm enclosed NMOSFETs and in PMOSFETs, at 100 Mrad total dose, noise degradation is negligible. This provides evidence for a model where the basic mechanism underlying noise increase in irradiated devices is associated to lateral parasitic transistors.

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Conclusions Nanoscale MOSFETs have very interesting new features in terms of device processing and physics. At the 90 nm and 65 nm nodes, low-noise analog design will pose challenges but, according to the study of key analog parameters, appears to be still viable. PMOSFETs appear to gradually lose their 1/f noise advantage over NMOSFETs. Isolation oxides are the main threat to ionizing radiation tolerance. Enclosed devices may still be necessary for low-noise performance under irradiation. The price of these technologies will of course have an impact on their use in our fields; this was beyond the scope of this talk.

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Backup slides

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Modeling lateral leakage From the I D,lat vs V GS curves for the equivalent parasitic transistor, it is possible to extract the product of its gate width and of its effective oxide capacitance W lat C OX,lat. This product increases with increasing dose, since a larger portion of the STI sidewall gets inverted. The effective gate width, oxide thickness and capacitance are determined by the extension of the inverted regions along sidewalls. At low doses, only the sidewall bottom is inverted because bulk doping is lower in that region; at higher doses the inversion region extends towards the surface, involving thinner STI oxide regions. gate STI W lat,finger t OX,lat,max t OX,lat,min θ Inverted region At STI sidewall TID induced positive charge P-type substrate gate STI W lat,finger θ Inverted region At STI sidewall TID induced positive charge P-type Substrate (Well) t OX,lat,max t OX,lat,min

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Effects of lateral leakage at different I D The radiation-induced increase of I D,lat appears to saturate beyond 10 Mrad. This may be due to a saturation effect in positive charge build-up in the STI oxide, along with a compensating effect from interface states. I D,lat goes from a weak inversion behavior (logI D linear with V GS ) to a strong inversion one (with a reduced slope of I D vs V GS ) at a smaller V GS than the drain current I D of the main device. The contribution of I D,lat to the total device current as well as the other effects due to lateral parasitic transistors are larger at small values of I D. Lateral leakage current Total drain current

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Lateral leakage in 130nm and 90nm core transistors The radiation-induced increase of I D,lat is considerably larger in 130 nm devices than in 90 nm transistors. This could be explained by a higher doping concentration in the p-type body for the 90 nm process, which mitigates the inversion of the surface along the STI sidewalls. Doping of P and N-wells increases with CMOS scaling, to keep drain/source depletion regions small with respect to gate length. More scaled CMOS technologies appear to be less sensitive to lateral leakage effects associated to the STI oxide. Enclosed devices may not be strictly required in rad-hard systems.

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, nm LP process: operating regions (preview) In terms of the g m /I D ratio, LP 65 nm transistors have an advantage over previous CMOS generation only at large drain current densities. This seems to point out that the device parameters (carrier mobility?) are optimized for large drive currents in digital circuits (large overdrive voltages)

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Radiation effects on noise: NMOS 130 nm open layout In 130 nm open layout NMOSFETs, at 10 Mrad total dose the main radiation effect is again a 1/f noise increase at low current density, due to the contribution of lateral parasitic devices. Since the impact of lateral devices is larger for this process, a noise increase in the white spectral region is also detected at low currents.

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, nm NMOS: white noise

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Channel thermal noise – STM 90 nm Equivalent channel thermal noise resistance slope  excess noise coefficient  w  w close to unity  no sizeable short channel effects in the considered operating regions (no data available for channel thermal noise in devices with L ≤ 0.13 m) Negligible contributions from parasitic resistances offset  noise contributions from parasitic resistors

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, Annealing In 90 nm transistors, contribution from sidewall leakage to the drain current disappears. Removal of radiation-induced positive charge from STI oxide switches off the lateral parasitic transistor and cancels its noise contribution. Annealing is instead only partially effective in 130 nm devices. 90 nm 130 nm

V. Re – 11 th Pisa Meeting on Advanced Detectors, Isola d’Elba, May 24 – 30, /f noise: gate stack fabrication process 1/f noise is systematically larger (not very sizably) in 90 nm Foundry B devices as compared with Foundry A transistors (see very different behavior of the gate leakage current: different level of nitridation in the oxide?).