CMOS VLSI Design Lecture 2: Fabrication & Layout Younglok Kim Sogang University Fall 2006

Outline Textbook: 3.1 ~ 3.3 CMOS Fabrication Gate Layout Standard Cell Layouts Stick Diagrams Wiring Tracks 2: Fab & Layout

CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process 2: Fab & Layout

Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors 2: Fab & Layout

Well and Substrate Taps Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps 2: Fab & Layout

Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line 2: Fab & Layout

Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal 2: Fab & Layout

Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2 2: Fab & Layout

Wafer Formation Czochralski method Pure polycrystalline Silicon Melting temperature A few degrees above the melting point (-1425°C) Atmosphere helium or argon Growth rate: 30~180 mm/hour Diameter of ingot depends on Seed withdrawal rate Seed rotation rate Wafer Cut of ingots of single-crystal silicon Flat scratch free mirror finish 2: Fab & Layout

Oxidation Grow SiO2 on top of Si wafer Wet oxidation 900~1000 C Water vapor Dry oxidation 1200 C Oxygen 2: Fab & Layout

Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light 2: Fab & Layout

Lithography Expose photoresist through n-well mask Strip off exposed photoresist 2: Fab & Layout

Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed 2: Fab & Layout

Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step 2: Fab & Layout

n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si 2: Fab & Layout

Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps 2: Fab & Layout

Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor 2: Fab & Layout

Polysilicon Patterning Use same lithography process to pattern polysilicon 2: Fab & Layout

Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact 2: Fab & Layout

N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing 2: Fab & Layout

N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion 2: Fab & Layout

N-diffusion cont. Strip off oxide to complete patterning step 2: Fab & Layout

P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact 2: Fab & Layout

Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed 2: Fab & Layout

Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires 2: Fab & Layout

Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of l = f/2 E.g. l = 0.3 mm in 0.6 mm process 2: Fab & Layout

Simplified Design Rules Conservative rules to get you started 2: Fab & Layout

Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4l / 2l, sometimes called 1 unit In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long 2: Fab & Layout

Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts 2: Fab & Layout

Example: Inverter 2: Fab & Layout

Example: NAND3 Horizontal N-diffusion and P-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 l by 40 l 2: Fab & Layout

Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers 2: Fab & Layout

Wiring Tracks A wiring track is the space required for a wire 4 l width, 4 l spacing from neighbor = 8 l pitch Transistors also consume one wiring track 2: Fab & Layout

Well spacing Wells must surround transistors by 6 l Implies 12 l between opposite transistor flavors Leaves room for one wire track 2: Fab & Layout

Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in l 2: Fab & Layout

Example: O3AI Sketch a stick diagram for O3AI and estimate area 2: Fab & Layout

Example: O3AI Sketch a stick diagram for O3AI and estimate area 2: Fab & Layout

Three Metal Layer CMOS 2: Fab & Layout