MAHATMA GANDHI INSTITUTE OF TECHNICAL EDUCATION & RESEARCH CENTER NAVSARI - Patel Richa ( )

Introduction The conventionalor standard TTL family was the first TTL family introduced,appearing in the mid-1960s. over the years,the performance of this family has improved and several other TTL families have been introduced. Another family introduction in the late 1960s is the low power TTL circuit. This configiration is basically the same as that of the conventional circuit but uses larger resistors to minimize input current requirements. While power dissipation per gate is decreased, so also is switching times and output drive current.

Family Typical Designation Average Power Dissipation/Gate (mW) Typical Propagation Delay(ns) Convention (Note 1) Low Power74L00133(Note 2) Schottky74S00203(Note 3) Low Power Schottky 74LS00210(Note 4) Advanced schottky 74AS0071.5(Note 5) Power Schottky74ALS0014(Note 5) Fast74F0043(Note 6) TABLE A1.1 Comparison Of Several TTL Logic Families

The schottky TTL family became prominent in the early 1970s. This circuit uses schottky diodes to clamp the base collector junctions of key transistors to prevent saturation of the transistor. Avoiding saturation of switching transistors decreases switching times, resulting in a higher speed circuit. Switching speeds are decreased by a factor of two or three over conventional TTL in the schottky circuit.

Low power schottky reduces the power dissiption of the schottky circuit by increasing the chip resistors and slightly modifying the basic current configuration. Advanced schottky and advance low power schottky were introduced around Advance schottky gates have lower switching times than does any other family of TTL circuits. Advanced low power schottky decreases power dissiption compared to conventional TTL by factor of ten while decreasing switching times by a factor of two or three

In addition to a change of input configuration, the advanced TTL families are fabricated with smaller device geometries to minimize parasitic capacitors that limit switching speeds. As fabrication technology improves, leading to comparable prices between TTL families, the lower performance circuits become obsolete. The advanced schottky families are becoming very prominet in the design of TTL systems.

Available Gates Although several thousands of gates can be integreted on a chip, SSI circuit contain only a maximum of three or four gates on each chip. This limitation is imposed by the number of pins allowed on the IC package. SSI chips generally limit the number of pins to 12,14, or 16. The power supply requres two connections to the chip(+5 v and ground), and each seprate gate requires an output and two inputs pins. The required power supply for TTL is 5 ± 0.25 v.

FIGURE A1.2 (a) Hex inverter (b) Quad two-input NAND (c) Triple three-inpute NOR (d)Dual four-inpute AND (e) Single eight-input NAND

Parameter Min Typ Max 74s 74s 74s Min Typ Max 74LS 74LS 74LS Min Typ Max Units V OH High-level output V OL Low-level output I IH High-level input 40 I IL Loe-level input -1.6 t pLH propagation delay 27 t pHL propagation delay V V 20 µA -0.4 mA 15 ns 20 ns TABLE A1.3 Electrical Characteristics of 74, 74S, and 74LS Table A1.3 summarizes several characteristics for a TTL AND gate. The characteristics correspond to three families of the 7408 quad two-input AND gate chip: the 74 family, the 74LS family, and the 74S family.

Descripation 74 74S 74LS 74s 74s 74s Min Nom Max 74LS 74LS 74LS Min Nom Max Units Inputes 1 ul 1 sul 1 Lsul Output 10 ul 10 sul 10 Lsul V 2.0 V 0.8 V -800 mA 8 mA Recommended Operating Condition Descripation 74 74S 74LS Inputes 1 ul 1 sul 1 Lsul Output 10 ul 10 sul 10 Lsul Input and Output Loading and Fan-Out Tables

Open Collector Gates In µP systems, it is not uncommon to drive a single input line with several different gate outputs. Figure A1.4 shown an arrangement with three NAND gates driving lines A and three NAND gates driving line B. With normal TTL gates, this arrangement is inappropriate and generally results in the destruction of some of the connected gates.

A B FIGURE A1.4 Multiple gates driving lines A and B