05-1 Digital Integrated Circuits 05: Advanced Fabrication & Lithography Revision 2009 01 23.

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Presentation transcript:

05-1 Digital Integrated Circuits 05: Advanced Fabrication & Lithography Revision

05-2 Advanced CMOS Processing Copper Metal Metal Gates High-K Dielectric

05-3 Damascene Process A B

05-4 Damascene Process C D

05-5 Damascene Process E F

05-6 Metal Gates Polysilicon gates Higher specific resistivity than metal Carrier depletion effects Metal Gates Must withstand high temperatures (self-aligned process) Must provide reasonable work function differences for both types of transistors (e.g. Ru for p-MOS, TaSiN for n-MOS)

05-7 High-K Dielectric SiO 2 Gate Insulator (  = 3.9) High purity, excellent interface At current device dimensions (tox = 2 nm), the oxide leakage current is excessive High-K Dielectric A thicker layer may be used with similar electrical characteristics

05-8 Lithography and Masks positive resist

05-9 Lithography Systems 45 nm NODE 193 nm ArF EXCIMER LASER 4X STEPPER PROJECTION 150 nm THICK RESIST QUARTZ MASKS

05-10 Pushing the Diffraction Limit MOS transistor structure MOS transistors with 25 nm gate lengths. Diffraction “limit”

05-11 Layout Design Rules

05-12 Defects and Circuit Yield

05-13 Burn-in and Accelerated Testing Burn-in is performed to screen-out parts with early failure Accelerated Testing is used to estimate failure rates under normal operating temperatures