1 Test of Electrical Multi-Chip Module for Belle II Pixel Detector DPG-Frühjahrstagung der Teilchenphysik, Wuppertal 2015, T43.1 Belle II Experiment DEPFET (DEPleted p-channel Field Effect Transistor) Surrounding Electronics for the PXD in Belle II Towards the final module The Electrical-Multi-Chip Module (EMCM) Summary and Outlook

Felix Müller, DPG T43.1, Wuppertal 2015 SuperKEKB upgrade Belle II Nano beam scheme  smaller beam size (~nm) & increased beam currents (x2)  L = 8 x cm -2 s -1 (40 times larger than in KEKB)  E e- = 7 (8) GeV & E e+ = 4 (3.5) GeV (  = 0.42 (KEK)  0.28 (SuperKEK))  E cm = GeV - Y (4S) Nano beam scheme  smaller beam size (~nm) & increased beam currents (x2)  L = 8 x cm -2 s -1 (40 times larger than in KEKB)  E e- = 7 (8) GeV & E e+ = 4 (3.5) GeV (  = 0.42 (KEK)  0.28 (SuperKEK))  E cm = GeV - Y (4S) positron (4 GeV) electron (7 GeV) 5.0 m 7.4 m Changes involving the Vertex Detector (VXD):  Four layers of Double Sided Si-Strip Detector (DSSD) with a larger radius  Two layers of DEPFET pixel detector (PXD) Changes involving the Vertex Detector (VXD):  Four layers of Double Sided Si-Strip Detector (DSSD) with a larger radius  Two layers of DEPFET pixel detector (PXD) Pixel Detector (PXD) 2 layers of DEPFET pixels R = 14 mm, 22 mm Pixel Detector (PXD) 2 layers of DEPFET pixels R = 14 mm, 22 mm

3 DEPFET (Depleted p-channel Field Effect Transistor) impinging particle Clear Turn on DEPFET source Gate Felix Müller, DPG T43.1, Wuppertal 2015

4 Clear A DEPFET is a MOSFET onto a sideward depleted silicon bulk → Low noise → Low power → High signal/noise-ratio → Non-destructive readout → Low noise → Low power → High signal/noise-ratio → Non-destructive readout internal amplification: g q  0.5 nA/e - internal amplification: g q  0.5 nA/e - 90 steps fabrication process 9 Implantations 19 Lithographies 2 Polysilicon layers 2 Aluminum layers 1 Copper layer Back side processing 90 steps fabrication process 9 Implantations 19 Lithographies 2 Polysilicon layers 2 Aluminum layers 1 Copper layer Back side processing DEPFET (DEPleted p-channel Field Effect Transistor) Felix Müller, DPG T43.1, Wuppertal 2015

5 Control and readout electronics Felix Müller, DPG T43.1, Wuppertal 2015 SWITCHER Fast voltage pulses up to 20 V to activate gate rows and to clear the internal gate JTAG for interconnectivity tests 64 output drivers for both gate and clear channels  address 32 matrix segments 768 rows  192 electrical rows  6 ASICs needed per module SWITCHER Fast voltage pulses up to 20 V to activate gate rows and to clear the internal gate JTAG for interconnectivity tests 64 output drivers for both gate and clear channels  address 32 matrix segments 768 rows  192 electrical rows  6 ASICs needed per module Drain Current Digitizer (DCD) Keeps the columns line potential constant 8 bit ADCs Compensates for pedestal current variation (2bit DAC) Programmable gain and BW 256 input channels (4 per module) Drain Current Digitizer (DCD) Keeps the columns line potential constant 8 bit ADCs Compensates for pedestal current variation (2bit DAC) Programmable gain and BW 256 input channels (4 per module) Data Handling Processor (DHP) Pedestal correction Common mode correction Data reduction using the zero suppression Triggered readout scheme introduces further data reduction Controls the Switcher sequence Data Handling Processor (DHP) Pedestal correction Common mode correction Data reduction using the zero suppression Triggered readout scheme introduces further data reduction Controls the Switcher sequence Kapton Flex cable Power Supply via soldered contacts and bond wires Data transmission via bond wires 4 layers, 48 cm Kapton Flex cable Power Supply via soldered contacts and bond wires Data transmission via bond wires 4 layers, 48 cm DEPFET Pixel i,j,v 768x250 pixel x 2

6 Towards the Final Module Felix Müller, DPG T43.1, Wuppertal 2015 Large DEPFET matrix 4 Switchers 3 DCDs 3 DHPs 1 DEPFET matrix (120x192 pixels) Complete set of ASICs 1 Switcher 1 DCD (Drain Current Digitizer) 1 DHP (Data Handling Processor) 1 DEPFET matrix (64x32 pixels) EMCM 6 Switchers 4 DCDs 4 DHPs 1 silicon subtrate

7 EMCM (Electrical-Multi-Chip Module) Felix Müller, DPG T43.1, Wuppertal 2015 Goal Design and build a fully functional Belle II half-ladder (module) without DEPFET Reasons Check if there is enough space for full circuit design, including passive components (decoupling capacitors & termination resistors for LVDS signals) Testpads in order to probe the signals and voltages of the ASICs directly (voltage drops, parasitic capacitances, resistances, check of signal integrity) Technological feasibility of the 3-metal (Al1, Al2, Cu) system Practice flip-chipping (soldering ASICs on pads) and off-module interconnection (Kapton flex cable) Is cupper required in the sensitive region (technological manufacturing reasons)

8 EMCM – Geometrical Overview Felix Müller, DPG T43.1, Wuppertal 2015 DEPFET Basically it is an electrically active prototype of a half-ladder Even beam tests are possible with small piggy-back matrix Test vehicle for metal system and electrical performance of periphery DCD Switcher DHP Features Similar metal system (3 layers) as final modules Circuitry at periphery (end-of-stave) 4DHPs, 4DCDs, 6 Switchers (additionally 1 DEPFET matrix) Power Supply, Slow control (JTAG) and High Speed Signals via Kapton flex cable Sensitive region for test structures (small DEPFET matrix; 32x64 pixels)

9 Matrix assembly Felix Müller, DPG T43.1, Wuppertal 2015 Optionally, a matrix can be attached on the EMCM The DEPFET matrix is electrically connected via wire-bonds Operate device and compare measurements to PCB-assembled test setups (performance, noise, Signal-to-noise, stability …) Drain lines are comparable with final modules ~45mm

10 EMCM, Periphery Felix Müller, DPG T43.1, Wuppertal 2015 Power Patch Panel EMCM Kapton Data Patch PanelCooling Aluminum Jig

11 Test Setup in Semiconductor Laboratory Felix Müller, DPG T43.1, Wuppertal 2015 Power Supplies EMCM DHHdata cables power cable cooling

12 W17-3, 305MHz Felix Müller, DPG T43.1, Wuppertal 2015 DHH DHP Switcher1 write switcher sequence into the DHP memory Switcher2 Switcher3 Switcher4 Switcher5 Switcher6 control sequence EMCM Bondwires

13 ~/ADC_curves/DCD_noise/15_01_13_DCDpp0_66th/scan Felix Müller, DPG T43.1, Wuppertal 2015 DCD W18-3 – Optimize Parameters (305MHz) LMU PS 1 DCD on (DCD 1) 4 DCDs on daciampbias = 66 dacifbpbias = 80 dacipsource = 88 dacipsource2 = 77 optimized parameters for noise minimum daciampbias = 64 dacifbpbias = 85 dacipsource = 82 dacipsource2 = 63

14 W18-3, ADC Transfer Curves - Gain Felix Müller, DPG T43.1, Wuppertal 2015

Felix Müller, DPG T43.1, Wuppertal 2015 DCD1 – Correlation (Pedestals, Noise)

16 Aurora Links – Signals Integrity Felix Müller, DPG T43.1, Wuppertal 2015 Module:DHPT Testboard Data rate:1.6 Gbit/s Cable length:15m Core Voltage:1.62V Bias15 BiasD150 Module:W17-3 – DHPT1 Data rate:1.6 Gbit/s Cable length:15m Core Voltage:1.64V Bias7 BiasD150

17 Summary and Outloot Felix Müller, DPG T43.1, Wuppertal 2015 Switchers work properly ADC transfer curves show expected gains DCD optimized (noise ~ 0.6ADUs) with LMU PS (all ASICs in operation) High Speed Aurora links partially established  High Speed Probe (data eyes)  Data chain, extract S-parameters Zero Suppressed Readout Matrix operation “Pilot run” (first complete module PXD9)

18 Backup Felix Müller, DPG T43.1, Wuppertal 2015

19 ADC transfer curve with DCD-Bv Felix Müller, DPG T43.1, Wuppertal 2015 RefIn=1.2V AmpLow=1.4V

20 SwitcherB18v2 Designed by University of Heidelberg Geometry: 1470µm x 3600µm 32 channel outputs (32 gates & 32 clears) for succussive row switching Provide fast voltage pulses up to 20V in order to active the gates and clear the internal gates JTAG for boundary scans and controlling termination resistors 768 rows => 192 electrical rows (4-fold-readout) => 6 ASICs Felix Müller, DPG T43.1, Wuppertal 2015

21 Drain Current Digitizer (DCD) Available Chips: DCDB DCDBv2 DCDBv4 DCDBPip(eline) Receive and digitizes DEPFET currents; placed at the edges of DEPFET sensor 256 analogue input channels 32 digital output channels (digitally processed and multiplexed to one 8-bit wide readout) Two cyclic ADCs (Anlogue-Digital-Converter) for sampling each channel alternately Bump bonded (soldered) UMC 180nm technology Geometry: 3240µm x 4969µm 1000 drains => 4 DCDs Pixel (n+1) Clear Pixel n Sample Gate Measured by Florian Lütticke (University of Bonn) Felix Müller, DPG T43.1, Wuppertal 2015

22 Drain Current Digitizer (DCD) Felix Müller, DPG T43.1, Wuppertal 2015

23 Data Handling Processor (DHP) Available ASIC DHP 0.2 New ASIC submitted DHPT 1.0 Geometry: 3280µm x 4200µm Raw Data Buffer Static Pedestal Correction (Noise Correction) Common Mode Correction Dynamic Pedestal Correction Zero Suppression Hit Pairing (FIFO1 + FIFO2) Framing (AURORA) Serializer + Gbit link driver (1.6Gbit/s) JTAG configuration (JTAG output to DCDs and Switcher) Switcher control 1.6GB output link per chip Overall memory size is 4 frames (2 raw data, 2 pedestals) Felix Müller, DPG T43.1, Wuppertal 2015

24 Matrix and surrounding ASICs High readout speed by four-fold rolling shutter mode  entire frame within 20µs The DEPFET matrix is split in two modules (half-ladders) doubling the readout electronics 768x250 pixels each ladder Felix Müller, DPG T43.1, Wuppertal 2015

25 Readout Electronics Drain currents from DEPFETs Digitalized by Drain Current Digitizers (DCDs) Data pre-processed by Data Handling Processors (DHPs) Power and data connection by a Kapton flex cable Further data processing at Data Handling hybrid (DHH) Via glass fibers to data acquisition system Felix Müller, DPG T43.1, Wuppertal 2015