A Synthesis Method for MVL Reversible Logic by 1 Department of Computer Science, University of Victoria, Canada M. Miller 1, G. Dueck 2, and D. Maslov 1 2 Faculty of Computer Science, University of New Brunswick, Canada

Outline - Motivation for our research - Definitions - Synthesis algorithm, results - Future work: templates, quantum implementation analysis page 1/18 ISMVL, Toronto, Canada May 20, 2004

Motivation page 2/18 Why reversible? Why MVL? ISMVL, Toronto, Canada May 20, 2004

Motivation page 2/18 Why reversible? For T equal room temperature, this package of heat is small, i.e. 2.9* Joule, but non-negligible. It can be calculated that for Madison Itanium-2 processor heat dissipation can be as high as W. Landauer's principle: logic computations that are not reversible, necessarily generate heat: kT*ln 2, for every bit of information that is lost, where k is Boltzmann's constant and T the temperature of the computation. ISMVL, Toronto, Canada May 20, 2004

Motivation page 3/18 Why reversible? Zhirnov et al. projected the heat dissipation due to the information loss calculation on the year 2016 in accordance to the ITRS They came up with the number W/cm 2. For comparison: regular light bulb – W surface of the sun – 6000 W/cm 2 estimated ultimate heat removal from silicon – 1000 W/cm 2 “no known solution” category – 93 W/cm 2 ISMVL, Toronto, Canada May 20, 2004

Motivation page 4/18 Why MVL? Reversible logic is often considered in conjunction with quantum computations. Why not binary? In NMR garbage is expensive. Consider a problem with input size In binary: bits are needed. In ternary: bits are needed. ISMVL, Toronto, Canada May 20, 2004

Motivation page 5/18 Why MVL? Reversible logic is often considered in conjunction with quantum computations. Why not continuous? Continuous transformations can only be approximated, thus errors accumulate. Distinction of two “close” amplitudes may be hard. How to code data? ISMVL, Toronto, Canada May 20, 2004

Definitions page 6/18 Definition. Multiple output MVL function is called reversible iff: is a bijection. In reversible logic fan-outs and feed-back conventionally are not allowed, thus any network is a cascade. The gates we use are those considered by De Vos and their simple extensions. ISMVL, Toronto, Canada May 20, 2004

Definitions: gates page 7/18 ISMVL, Toronto, Canada May 20, 2004 xNC1C Gates N and C1 were initially considered by De Vos. We introduce gate C2 and allow many controls. G G N-C1-C2 CN-CC1- CC2

Optimal Synthesis page 8/18 ISMVL, Toronto, Canada May 20, 2004 gatesC1-CNC1 CC1-CN C1-N CC1-CN C1-C2-N CC1-CC2-CN ,3423, ,7775,69215, ,92420,99257,951 72,39518,08963,292144,039 86,10747,849128,159127, ,66099,576118,63514, ,268126,98123, ,14558, ,2373, , , , Avg

More gates page 9/18 ISMVL, Toronto, Canada May 20, 2004 xDE We need gate D for synthesis. Further, allow controls to be either 1 or 2.

Synthesis Algorithm page 10/18 ISMVL, Toronto, Canada May 20, 2004 The Algorithm Assume the function is given in a truth table as a reversible specification. Transform output to the form of the input pattern by pattern assigning gates at either end of the cascade. Transform the output pattern to the form of input in lexicographical order. While working with the pattern of higher order do not affect patterns with lower order.

Synthesis Algorithm ISMVL, Toronto, Canada May 20, N C D transformgate choice 0  1 C1, E 0  2 C2, N 1  0 C2, E 1  2 D 2  0 C1, N 2  1 D page 11/18

Synthesis Algorithm: results ISMVL, Toronto, Canada May 20, 2004 GatesAlgorithm f onlyAlgorithm f and f -1 Optimal ,3952,5933, ,74312,95425, ,75539,061114, ,21780,699187, ,192103,66332, ,97879, ,88634, ,8498, ,2461, Avg page 12/18

ISMVL, Toronto, Canada May 20, 2004 Synthesis Algorithm: results Irreversible example: 3-bit ternary full adder. page 13/18

Future work: templates ISMVL, Toronto, Canada May 20, 2004 A size m template is a cascade of m gates which realizes the identity function. Any template of size m should be independent of smaller size templates, i.e. application of smaller templates does not decrease the number of gates in a size m template. Given G 0 G 1 …G m-1, a template of size m, its application for parameter p, is: - for page 14/18

Future work: templates ISMVL, Toronto, Canada May 20, 2004 A B C D E F G Example. Template ABCDEFG. p=4. Starting gate B. Direction: backward. B B A A G G F F C C D D E E Proper classification and application of the templates would help circuit simplification. page 15/18

Future work: templates ISMVL, Toronto, Canada May 20, 2004 page 16/

Future work: quantum cost ISMVL, Toronto, Canada May 20, 2004 Ternary constants: Circuit is applied to 2 ‘quantum computers’ in parallel. After computation, ternary 1 is measured on the 1 st and ternary 2 on the 2 nd ‘computer’. page 17/18

Future work: quantum cost ISMVL, Toronto, Canada May 20, 2004 Ternary gates: D and E can be decomposed into circuits with N, C1, and C2. page 18/18

END Thanks for Your attention! A Synthesis Method for MVL Reversible Logic