Uniboard – IP & Methodology Uniboard – IP and Methodology Chris Shenton University Of Manchester 26 th February 2009

Uniboard – IP & Methodology Tools & Methodology VHDL or Verilog – is there any benefit in mandating which hdl? Coding standards – lets have one… IP Repository available to all contributors Quality control of submitted IP –HDL Code Analysis Tools – Atrenta Spyglass or Mentor Graphics HDL Designer Design Reuse –Reuse Methodology Manual + Rule decks. Generic HDL with IP Wrappers – avoid primitive inference. Industry standard synthesis tools – no FPGA vendor specific versions.

Uniboard – IP & Methodology Tools CVS or Subversion Structural Design Tools –Mentor Graphics HDL Designer –Translogic EASE –Not Hand Crafted Tools – use industry standard generic tools whenever possible