Jean-Marie Bussat/Patrick Pangaud – July 9, FPPA design methodology  Intersil methodology  FPPA design constraints  "Symbolic" versus "Full"  FPPA98-FPPA2000 design flow  FPPA2001 design flow Outline

Jean-Marie Bussat/Patrick Pangaud – July 9, Intersil methodology Intersil (formerly Harris) uses the Cadence software bundled with several thousand lines of Skill code (Cadence scripting language)  Result called "Fastrack" design simulation Models based on process parameters OK ? modify design Monte-carlo simulation mean σ Statistical information about the process variations OK ? Layout design and verification Parasitic simulations OK ? GDS no yes

Jean-Marie Bussat/Patrick Pangaud – July 9, FPPA design "constraints" Problem: Instersil had a bad experience with its custom IC program: Some "big" customers had non-working designs and blamed Intersil for that.  Bad publicity for the foundry.  To prevent this to happen again Intersil don't want to deal directly with customers anymore. Customers must submit design ideas to Design House. The design house do the design and submit it to foundry  This method doesn't work for the FPPA: Design too specific... To much interaction needed between the engineer who has the design idea and the "real" designer. Must be the same person.  But Intersil do not want to give away Fastrack (Fastrack means direct access to the foundry).

Jean-Marie Bussat/Patrick Pangaud – July 9, FPPA design "constraints" (cont.) Agreement: We can do the design ourselves but we must interact with a design house (SdM, Charleroi, Belgium). SdM duties: - Provide a simplified Design Kit based on Fastrack.  missing devices = Semi-custom library: components are seen as black boxes - Provide simplified typical simulation models.  wrong models - Do Monte-Carlo simulations.  wrong simulations - Perform parasitic extraction and simulation. - Do final checking of the design. - Convert our design database into final Fastrack database.  conversion errors  Many problems came with this simplified Design Kit: - Incomplete kit - Bugs - Poor user's interface - Request for modification

Jean-Marie Bussat/Patrick Pangaud – July 9, "Symbolic" versus "full" "Symbolic" layout view"Full" layout view NPN transistor 5µ  1.3µ (smallest transistor in UHF1-X) 58 µ 48 µ From the simplified design kitAs in Fastrack

Jean-Marie Bussat/Patrick Pangaud – July 9, FPPA98 - FPPA2000 design flow design simulation OK ? modify design Monte-carlo simulation OK ? Layout design and verification Parasitic simulations OK ? GDS no yes Simplified typical models Simplified design (symbolic) library yes GDS Conversion tool + Final verification "Symbolic" design database SdM /

Jean-Marie Bussat/Patrick Pangaud – July 9, FPPA2000 fix  FPPA2001 Tests and investigations prove that parasitic resistors are the main cause of encountered problems.  Parasitic resistor extraction not part of the symbolic design kit.  We wrote our own set of extraction rules based on technology specifications  Proper layout design verification needs a lot of iterations between layout edition and parasitic extraction.  Got SdM to provide the full set of extract rules  Added still missing parasitic resistor extraction  Replaced symbolic layout view by their real counterpart (needed to be able to use the full set of extract rules) New design kit provide capability of extracting both parasitic resistors and capacitors. Parasitic resistance extraction checked by hand calculations and comparison between parasitic simulation results and measurement results.

Jean-Marie Bussat/Patrick Pangaud – July 9, FPPA2001 design flow design modifications simulation OK ? modify design Monte-carlo simulation OK ? Layout redesign and verification Parasitic simulations OK ? no yes Simplified typical models yes GDS SdM / GDS Final Layout FPPA2000 Full extract rules Parasitic resistor extract rules Updated design kit Final design database Final verification with Fastrack and release to foundry