Design & Co-design of Embedded Systems Introduction to System-Level Modeling in SystemC 2.0 Maziar Goudarzi

Fall 2005 Design & Co-design of Embedded Systems2 Today Program zA Brief Review of SystemC 1.0 zObjectives of SystemC 2.0 zCommunication and Synchronization in SystemC 2.0 zModels of Computation within SystemC Reference: Stuart Swan, “An Introduction to System-Level Modeling in SystemC 2.0,” Cadence Design Systems, 2001.

Fall 2005 Design & Co-design of Embedded Systems3 Brief Review of SystemC 1.0 zA set of modeling constructs in RTL or Behavioral abstraction level zStructural design using Modules, Ports, and Signals zRich set of data types including bit-true types ySpecially: Fixed-Point data types for DSP apps.

Fall 2005 Design & Co-design of Embedded Systems4 Brief Review of SystemC 1.0 (cont’d) zConcurrent Behavior is described using Processes yProcesses can suspend and resume execution yLimited control over awakening events xEvents and sensitivity list are static ( specified at compile-time) zSC_THREAD and SC_CTHREAD processes yCan suspend and resume execution yRequire their own execution stack yMemory and Context-switching time overhead ySC_METHOD gives best simulation performance

Fall 2005 Design & Co-design of Embedded Systems5 Brief Review of SystemC 1.0 (cont’d) zHardware Signals are hard to model in software  Initialization to X xUsed to detect reset problems  sc_logic, sc_lv data types yMultiple drivers  resolved logic signals ( sc_signal_rv ) yNot immediately change their output value xDelay is essential xCapability to swap two registers on clock edge

Fall 2005 Design & Co-design of Embedded Systems6 Brief Review of SystemC 1.0 (cont’d) zDelayed assignment and delta cycles yJust like VHDL and Verilog yEssential to properly model hardware signal assignments xEach assignment to a signal won’t be seen by other processes until the next delta cycle xDelta cycles don’t increase user-visible time xMultiple delta cycles may occur

Introduction to System-Level Modeling in SystemC 2.0 Objectives of SystemC 2.0

Fall 2005 Design & Co-design of Embedded Systems8 Objectives of SystemC 2.0 zPrimary goal: Enable System-Level Modeling ySystems include hardware, software, or both yChallenges: xWide range of design models of computation xWide range of design abstraction levels xWide range of design methodologies

Fall 2005 Design & Co-design of Embedded Systems9 Objectives of SystemC 2.0 (cont’d) zSolution in SystemC 2.0 yIntroduces a small but very general purpose modeling foundation => Core Language yElementary channels xOther library models provided (FIFO, Timers,...) xEven SystemC 1.0 Signals ySupport for various models of computation, methodologies, etc. xBuilt on top of the core language, hence are separate from it

Introduction to System-Level Modeling in SystemC 2.0 Communication and Synchronization in SystemC 2.0

Fall 2005 Design & Co-design of Embedded Systems11 Communication and Synchronization zSystemC 1.0 Modules and Processes are still useful in system design zBut communication and synchronization mechanisms in SystemC 1.0 (Signals) are restrictive for system-level modeling yCommunication using queues ySynchronization (access to shared data) using mutexes

Fall 2005 Design & Co-design of Embedded Systems12 Communication and Synchronization (cont’d) zSystemC 2.0 introduces general-purpose yChannel xA container for communication and synchronization xThey implement one or more interfaces yInterface xSpecify a set of access methods to the channel But it does not implement those methods yEvent xFlexible, low-level synchronization primitive xUsed to construct other forms of synchronization

Fall 2005 Design & Co-design of Embedded Systems13 Communication and Synchronization (cont’d) zOther comm. & sync. models can be built based on the above primitives yExamples xHW-signals, queues (FIFO, LIFO, message queues, etc) semaphores, memories and busses (both at RTL and transaction-level models)

Fall 2005 Design & Co-design of Embedded Systems14 Communication and Synchronization (cont’d) Channel Module1Module2 Events Interfaces Ports to Interfaces

Fall 2005 Design & Co-design of Embedded Systems15 SystemC 2.0 Language Architecture z All built on C++ z Upper layers cleanly built on lower ones z Core language yStructure yConcurrency yCommunication ySynchronization z Data types separate from the core language z Commonly used communication mechanisms and MOC built on top of core language z Lower layers can be used without upper ones

Fall 2005 Design & Co-design of Embedded Systems16 A Communication Modeling Example: FIFO FIFO ProducerConsumer Write Interface Read Interface Problem definition: FIFO communication channel with blocking read and write operations Source available in SystemC installation, under “ examples\systemc ” subdirectory

Fall 2005 Design & Co-design of Embedded Systems17 FIFO Example: Declaration of Interfaces class write_if : public sc_interface { public: virtual void write(char) = 0; virtual void reset() = 0; }; class read_if : public sc_interface { public: virtual void read(char&) = 0; virtual int num_available() = 0; }; FIFO pc

Fall 2005 Design & Co-design of Embedded Systems18 FIFO Example: Declaration of FIFO channel class fifo: public sc_channel, public write_if, public read_if { private: enum e {max_elements=10}; char data[max_elements]; int num_elements, first; sc_event write_event, read_event; bool fifo_empty() {…}; bool fifo_full() {…}; public: SC_CTOR(fifo) { num_elements = first=0; } void write(char c) { if ( fifo_full() ) wait(read_event); data[ ]=c; ++num_elements; write_event.notify(); } void read(char &c) { if( fifo_empty() ) wait(write_event); c = data[first]; --num_elements; first = ; read_event.notify(); } FIFO pc

Fall 2005 Design & Co-design of Embedded Systems19 Declaration of FIFO channel (cont’d) void reset() { num_elements = first = 0; } int num_available() { return num_elements; } };// end of class declarations FIFO pc

Fall 2005 Design & Co-design of Embedded Systems20 FIFO Example (cont’d) zAll channels must  be derived from sc_channel class xSystemC internals (kernel\sc_module.h) typedef sc_module sc_channel;  be derived from one (or more) classes derived from sc_interface yprovide implementations for all pure virtual functions defined in its parent interfaces

Fall 2005 Design & Co-design of Embedded Systems21 FIFO Example (cont’d) zNote the following extensions beyond SystemC 1.0  wait() call with arguments => dynamic sensitivity  wait(sc_event) xwait(time) // e.g. wait(200, SC_NS); xwait(time_out, sc_event) //wait(2, SC_PS, e); yEvents xare the fundamental synch. primitive in SystemC 2.0 xUnlike signals, have no type and no value always cause sensitive processes to be resumed can be specified to occur: –immediately/ one delta-step later/ some specific time later

Fall 2005 Design & Co-design of Embedded Systems22 The wait() function // wait for 200 ns. sc_time t(200, SC_NS); wait( t ); // wait on event e1, timeout after 200 ns. wait( t, e1 ); // wait on events e1, e2, or e3, timeout after 200 ns. wait( t, e1 | e2 | e3 ); // wait on events e1, e2, and e3, timeout after 200 ns. wait( t, e1 & e2 & e3 ); // wait for 200 clock cycles, SC_CTHREAD only (SystemC 1.0). wait( 200 ); // wait one delta cycle. wait( 0, SC_NS ); // wait one delta cycle. wait( SC_ZERO_TIME );

Fall 2005 Design & Co-design of Embedded Systems23 The notify() method of sc_event zPossible calls to notify(): sc_event my_event; my_event.notify(); // notify immediately my_event.notify( SC_ZERO_TIME ); // notify next delta cycle my_event.notify( 10, SC_NS ); // notify in 10 ns sc_time t( 10, SC_NS ); my_event.notify( t ); // same

Fall 2005 Design & Co-design of Embedded Systems24 Completing the Comm. Modeling Example SC_MODULE(producer) { public: sc_port out; SC_CTOR(producer) { SC_THREAD(main); } void main() { char c; while (true) { out->write(c); if(…) out->reset(); } } }; SC_MODULE(consumer) { public: sc_port in; SC_CTOR(consumer) { SC_THREAD(main); } void main() { char c; while (true) { in->read(c); cout num_available(); } } }; FIFO pc

Fall 2005 Design & Co-design of Embedded Systems25 Completing the Comm. Modeling Example (cont’d) SC_MODULE(top) { public: fifo *afifo; producer *pproducer; consumer *pconsumer; SC_CTOR(top) { afifo = new fifo(“Fifo”); pproducer=new producer(“Producer”); pproducer->out(afifo); pconsumer=new consumer(“Consumer”); pconsumer->in(afifo); }; FIFO pc

Fall 2005 Design & Co-design of Embedded Systems26 Completing the Comm. Modeling Example (cont’d) zNote: yProducer module xsc_port out; Producer can only call member functions of write_if interface yConsumer module xsc_port in; Consumer can only call member functions of read_if interface e.g., Cannot call reset() method of write_if yProducer and consumer are xunaware of how the channel works xjust aware of their respective interfaces yChannel implementation is hidden from communicating modules

Fall 2005 Design & Co-design of Embedded Systems27 Completing the Comm. Modeling Example (cont’d) zAdvantages of separating communication from functionality yTrying different communication modules yRefine the FIFO into a software implementation xUsing queuing mechanisms of the underlying RTOS yRefine the FIFO into a hardware implementation xChannels can contain other channels and modules Instantiate the hw FIFO module within FIFO channel Implement read and write interface methods to properly work with the hw FIFO Refine read and write interface methods by inlining them into producer and consumer codes

Introduction to System-Level Modeling in SystemC 2.0 Models of Computation within SystemC

Fall 2005 Design & Co-design of Embedded Systems29 Models of Computation within SystemC zMany different models yThe best choice is not always clear zBasic topics in a computation model yThe model of time, and event ordering constraints xTime model (real valued, integer-valued, untimed) xEvent ordering (globally ordered, partially ordered) ySupported methods of communication between concurrent processes yRules for process activation

Fall 2005 Design & Co-design of Embedded Systems30 Models of Computation within SystemC (cont’d) zSystemC 2.0 yGeneric model of computation xThe designer can (and is to) implement his desired model y(Virtually) all discrete-time models are supported xStatic Multi-rate Data-flow xDynamic Multi-rate Data-flow xKahn Process Networks xCommunicating Sequential Processes xDiscrete Event as used for RTL hardware modeling network modeling (e.g. stochastic or “waiting room” models) transaction-based SoC platform-modeling ynot suitable for continuous-time models (e.g. analog modeling)

Fall 2005 Design & Co-design of Embedded Systems31 Models of Computation within SystemC (cont’d) zProof of generic usage of SystemC 2.0 primitives ySignals are realized on top of channels, interfaces, and events

Fall 2005 Design & Co-design of Embedded Systems32 Future Evolution of SystemC zExpected to be SystemC 3.0 ySupport for RTOS modeling yNew features in the core language xFork and join threads + dynamic thread creation xInterrupt or abort a thread and its children xSpecification and checking of timing constraints xAbstract RTOS modeling and scheduler modeling zExpected to be SystemC 4.0 yNew features in the core language xSupport for analog mixed signal modeling

Fall 2005 Design & Co-design of Embedded Systems33 Future Evolution of SystemC (cont’d) zExtensions as libraries on top of the core language yStandardized channels for various MOC (e.g. static dataflow and Kahn process networks) yTestbench development xLibraries to facilitate development of testbenches data structures that aid stimulus generation and response checking functions that help generate randomized stimulus, etc. ySystem level modeling guidelines xlibrary code that helps users create models following the guidelines yInterfacing to other simulators xStandard APIs for interfacing SystemC with other simulators, emulators, etc.

Fall 2005 Design & Co-design of Embedded Systems34 Today Summary zCommunication and synchronization primitives introduced in SystemC 2.0 sc_channel sc_interface sc_event zThe language architecture is changed ySmall, general-purpose core y=> support various system-level design methodologies and MOCs zMinor other new additions exist yReference: “Functional Specification for SystemC 2.0,” available in the SystemC distribution

Fall 2005 Design & Co-design of Embedded Systems35 Assignments zAssignment 5 1.Develop a design consisting of two modules communicating through a channel. One module reads a file and sends it to the other module who saves it in another file. 2.Refine the design such that the channel is replaced with a hardware FIFO yDue Date: Tuesday (next week), Azar 8th