DEVELOPMENTS ON ATLAS PIXEL DETECTORS Patrick Pangaud Centre de Physique des Particules de Marseille C.P.P.M 163, avenue de Luminy Case Marseille cedex 09 France 5th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS1

OUTLINE Hybrid Pixels Detector for High Energy Physics Atlas developments IBM 130nm : FE-I4 development TSMC 65nm : FE-x5 developments TEZZARON 3-D 130nm: FE-TC4 developments Global Foundries 130nm : FE-C4 developments Monolithic Pixels Detector for High Energy Physics Smart pixel (monolithic) Global Foundries 130nm : HV-CMOS development 25th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS

Hybrid Pixels Detector for particles trackers 35th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS An early 3-D approach!! Sensor for particles detection Dedicated electronic chip AND A bump-bonding solder for interconnection  Sensors (Si, CdTe, GaAs, Diamond…) for ionizing particles Electronic pixel readout Monolithic device Analog detection (low noise, low power) Discriminator Digital readout

Hybrid Pixels Detector for LHC/HL-LHC at CERN 45th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS LHC : Luminosity of cm -2.s -1 HL-LHC expected 10 times more luminosity, more pixels, more ionizing particles, more … !!! Whatever will be discovered in next years at LHC, need much data to understand what has been discovered. Higher luminosity allows extending discovery/studies to higher masses processes of lower cross-section LHC has plans of upgrade by increasing luminosity to collect ultimately ~ 3000 fb -1. This will open new physics possibilities.

LHC and ATLAS upgrade 5 5th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS ∫ L dt Year phase-0 phase-1 phase /142018~ TeV → 14 TeV → 2x10 33 cm -2 s -1 → 1x10 34 cm -2 s -1 1x10 34 → ~2x10 34 cm -2 s -1 Now ~10 fb -1 ~50 fb -1 ~300 fb fb -1 → 5x10 34 cm -2 s -1 luminosity leveling Possible upgrade timeline T. Kawamoto, TIPP2011, Chicago, USA ATLAS needs to maintain excellent position resolution (vertexing, tracking)

Inner Tracking ATLAS detector 65th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS Straw tubes Silicon strip Silicon pixel

IBM 130nm FE-I4 development 75th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS HYBRID PIXELS SENSOR FOR HIGH ENERGY PHYSICS

ATLAS upgrade : phase th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS IBL technology Planner silicon sensor 3-D silicon sensor Diamond sensor → postponed for future upgrade Double side 3D sensor Planner sensor prototype New readout chip of higher performance T. Kawamoto, TIPP2011, Chicago, USA Existing B-layer Newbeam pipe IBL mounted on beam pipe

Hybrid Pixels Sensor for HEP The FE-I4 readout chip 95th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS 50 μm FE-I3 CMOS technology : 250 nm 400 μm 250 μm FE-I4 CMOS technology : 130 nm Done : ATLAS/LHC (2008/2009) Under Production ATLAS/LHC upgrade project ( ) FE-I3 FE-I4 Participating institutes: Bonn Bonn: D. Arutinov, M. Barbero, T. Hemperek, A. Kruth, M. Karagounis. CPPM CPPM: D. Fougeron, M. Menouni. Genova: Genova: R. Beccherle, G. Darbo. LBNL LBNL: S. Dube, D. Elledge, M. Garcia-Sciveres, D. Gnani, A. Mekkaoui. Nikhef Nikhef: V. Gromov, R. Kluit, J.D. Schipper

FE-I4 : Motivation for Redesign of FE 105th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS Need for a new FE? Smaller b-layer radius + potential luminosity increase  higher hit rate.  FE-I3 column-drain architecture saturated.  FE-I4 new digital architecture: local regional memories, stop moving hits around (unless RO).  FE-I4 has smaller pixel (reduced cross-section). New technology:  Higher integration density for digital circuits, rad-hard, availibility μm  130 nm FE-I3  FE-I4 Hit prob. / DC Inefficiency [%] LHC IBL sLHC FE-I3 at r=3.7 cm! The “inefficiency wall” M. Backhaus, FEI4 course, Desy, Germany

Motivation for Redesign of FE 115th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS Need for a new FE? Accommodate higher hit rate (smaller b-layer radius + luminosity increase)  Architecture based on local memories (no column-drain mechanism). Smaller pixel size: enhanced granularity and reduced cross-section. Reduced periphery & bigger chip: higher active area fraction (<75%  ~90%); cost down for sLHC (main driver is flip-chip, costs per chip). Big chip a challenge: power (routing, start-up), clk. distrib., yield… Simple module: No Module Controller  More digital functions into the FE. Power efficient design & new concepts: Analog design for reduced currents; decrease of digital activity (digital logic sharing for neighbor pixels); new powering concepts. 8 metal layers [2 thick Alu.]  Power routing. New technology: Higher integration density for digital circuits, radiation-hardness (no Enclosed Layout Transistor), availability on timescales of our experiments. M. Backhaus, FEI4 course, Desy, Germany

ATLAS upgrade : phase th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS The current B-layer will become inefficient after phase-1 (beyond nominal luminosity): data bandwidth, radiation damages, … The idea is, instead of replacing the B-layer, which is very difficult and dangerous, add a new B-layer inside the present one. 3 pixel layers → 4 pixel layers Insert the new layer inside the current beam pipe (Insertable B-Layer → IBL) using a smaller beam pipe. Phase-1 was initially in 2016, now it is postponed to 2017 or 2018, → Advance the project schedule and install in 2013/2014. it helps anyway, improves performance less activation in earlier time (ease of installation) T. Kawamoto, TIPP2011, Chicago, USA Existing B-layer Newbeam pipe IBL mounted on beam pipe

TSMC 65nm FE-x5 development TEZZARON 3-D AND GLOBAL FOUNDRIES 130nm FE-TC4 development FE-C4 development 135th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS HYBRID PIXELS SENSOR FOR HIGH ENERGY PHYSICS

Motivations for ATLAS read-out chip upgrades – Phases 1 and 2 145th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS Improve spatial resolution Deal with an increasing counting rate Decrease pixel size 50 μm 250 μm FE-I4, 130nm Technology shrinking 3-D benefits : Pixel size reduction Functionalities splitting Technologies mixing Vertical stacking 125 μm 50 μm FE-TC4, 130 nm DIGITAL ANALOG 400 μm 50 μm FE-I3, 250 nm First MPW run for High Energy Physics organized by FNAL with a consortium of 15 institutes. The proposed 3-D process combines : GLOBAL FOUNDRY 130nm technology TEZZARON 3D technology 25 μm 100 μm FE-x5, 65nm

65nm technology -> FE-x5 155th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS

Tezzaron-Chartered 3-D technology 165th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS Main characteristics : 2 wafers (tier 1 and tier 2) are stacked face to face with Cu- Cu thermo-compression bonding Via Middle technology : Super-Contacts (Through Silicon contacts) are formed before the BEOL of Chartered technology. Wafer is thinned to access Super-Contacts Chartered 130nm technology limited to 5 metal levels Back-side metal for bonding (after thinning) One tier Bond interface layout Wafer to wafer bonding

Fermilab 3-D Multi-Project Run 175th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS  Fermilab has planned a dedicated 3-D multi project run using Tezzaron for HEP during 2009  There are 2 layers of electronics fabricated in the Global Foundries 0.13 um process, using only one set of masks. (Useful reticule size 15.5 x 26 mm)  The wafers are bonded face to face. ATLAS/HL-LHC Sub-part

Fermilab 3-D Multi-Project Run : C-Band ATLAS 185th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS FE-TC4-AE SEU-3D FE-TC4-DS SEU-3D TSV Daisy Chain + BI Electrical Test TSV vs Transistors Electrical Test TSV vs Transistors Electrical Test TSV vs Transistors + capacitors Electrical Test TSV vs Transistors + capacitors Mechanical stress DFF + Trans + Cap Mechanical stress DFF + Trans + Cap  FETC4-AE (CPPM) : same than FEC4_P1,  FETC4-DS (CPPM) : Shift Register + counter + readout data and ”Drum registers“  SEU-3D (CPPM) : SEUless memories blocks  General test structures (CPPM) : TSV + BI Daisy chain (electrical parameters) ; TSV capacitors value with and without BackMetal and BI ; Transistors (Linear and ELT) closed to TSV ; Mechanical stress effects of devices (Trans, Cap, Res, DFF)

Fermilab 3-D Multi-Project Run : D-Band ATLAS 195th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS FE-TC4-AE FE-TC4-DC OmegaPix Analog OmegaPix Analog OmegaPix Digital OmegaPix Digital Electrical Test TSV vs Transistors TSV, Cap and Bump Electrical Test TSV vs Transistors TSV, Cap and Bump Electrical Test TSV vs Transistors Electrical Test TSV vs Transistors  FETC4-AE (CPPM) : same than FEC4_P1  FETC4-DC (Bonn-CPPM) : Digital pixels Read-out "à la FEI4“  OmegaPix (LAL) : a 50x50 µm matrix pixel size  General test structures (CPPM) : TSV + BI Daisy chain (electrical parameters) ; TSV capacitors value with and without BackMetal and BI ; Transistors (Linear and ELT) closed to TSV ; Mechanical stress effects of devices (Trans, Cap, Res, DFF)

3-D project steps First 3-D design (MPW organized by FNAL) FE-TC4_P1 project Global Foundries 130 nm (5 metal levels) + Tezzaron One Tier for the analogue pixel part : 14x61 pixel matrix Pixel size : 50x166µm One Tier for the digital part Two versions have been designed : one dedicated for test, (FE-TC4-DS) one “FE-I4-like”.,(FE-TC4-DC) 205th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS July 09 / now Submission / Test

FE-TC4-AE analogue tier 215th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS Based on FE-C4_P1 chip + all adds for 3-D connection Input signal from sensor via the Super-Contacts Bonding pad in Back-side metal 2 possible ways for discriminator output read-out: With the simple read-out part existing yet into the pixel With the tier 2 (via the Bond Interface) Additional switch for read-out

FE-TC4-DS digital tier for test : parasitic coupling study between tiers 225th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS Analogue tier and digital tier are face to face (sensitive part facing digital part). FE-TC4-DS : dedicated for parasitic coupling studies between the 2 tiers. 3 functions : Read the discriminator output Generate noise (digital commutations) in front of 11 specific areas of the analogue pixel (preamplifier, feed-back, amplifier2, DAC…) Test different shielding configurations. Analogue pixel layout : 11 specific areas ANALOGUE DIGITAL

FE-TC4-P1 test results : 3-D Chips 235th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS We received individual tiers at the beginning of These individual tiers are not 3-D connected together. The FETC4-AE analog tier has similar results as FEC4_P1 chip with radiation tolerance up to 240MRads. The FETC4_DS and FETC4_DC digital tiers work (not irradiated at the moment). The SEU-3D chip works well with protons radiation tolerance up to 400Mrads. Mean Threshold versus dose , FE-C4_P1 FE-TC4_AE_1 FE-TC4_AE_2 FE-TC4_AE_ Dose (MRad) Mean Threshold (e-) The full 3-D chips arrived during summer Two kinds of chips were tested. The analog and digital tiers of the FETC4-AEDS and FETC4-AEDC chips work individually but no data exchange have been demonstrated. The analog tier shows very good results. Untuned Threshold dispersion value 226 e- and noise lower than 100 e-.

The FE-TC4 ATLAS full-scale chip 245th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS FE-TC4, run 3-D Very large matrix size : 336 x 160 pixels Chip size of 18.8 x 20.1 mm mm End Of Column width. Small pixel size : 125µm x 50µm Bump bond pads compatible with 250 µm sensor pitch (FE-I4 project) The FE-TC4 re-uses main blocks of FE- I4 to be compatible for sensors, bump bonding, module/stave integration, testing tools, software, mechanics FE-I3 FE- TC Thanks to W.Wei (IHEP) for his collaboration by helping the design ( improvement of the pixel definition, global simulation by using Ultrasim and drafting the final Matrix)

2-D Project steps 255th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS Submission / Test March 08 / Summer 08 February 09 / April 09 FEI4_P1 design : IBM 130nm, 8 metals 14x61 "analogue" pixel matrix Pixel size : 50x166µm Rad-hard and SEU tolerance FEC4_P1 circuit : 2D Chartered 130nm, 8 metals Pixel structure : identical to FEI4_P1 (due to schedule no optimization has been done) Objectives : test Chartered technology (functionalities, performances, radiation…) FEC4_P2 circuit : 2D Chartered, 8 metals Based on FEC4_P1 circuit, plus : Optimization of transistors New latches for irradiation tests New PadRing strategy and ground/substrate separation FEC4_P3 : 2D Chartered, 8 metals but only 5 are used) Smaller pixel size : 50µm x 125µm Design of new sub-circuits and functionalities : Analogue multiplexor and Triple redundancy memory Calibration (pulse generator) PLL LVDS and ESD I/O Pads Nov 09 / Jan 10 Nov 10 / Nov 11 Thanks to N. Wang, J.Luo, W.Wei (IHEP)for their collaborations

FE-C4_Px test results All prototypes showed excellent results Un-tuned threshold dispersion around 200 e- Noise lower than 100 e- rms Power consumption 27µA/pixel 265th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS Irradiation performed at CERN/PS facility (24 GeV protons) Thanks to W.Zheng (IHEP), Z.Lei (USTC) for their collaborations 61x14 array

GLOBAL FOUNDRY 130NM HV-CMOS DEVELOPMENT 275th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS HYBRID PIXELS SENSOR FOR HIGH ENERGY PHYSICS

SMART Diode in CMOS technology 285th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS The CMOS signal processing electronics are placed inside the deep-n-well. PMOS are placed directly inside n-well, NMOS transistors are situated in their p-wells that are embedded in the n-well as well. Expected signal : Mips of 2000e- ( by increasing the substrate resistivity) Can we mix the smart diode and the 3D Integrated technology? We will submit soon a 1 st prototype smart pixels with the 3D Tezzaron-Global Foundries Technology Ivan Peric, FEE2011, Bergamo, Italy

Summary Since 20 years, the CPPM develops and tests hybrid pixel detectors for HEP and others applications. We are interested to develop future detectors having very small size of pixel with more functionalities, less matter, new improvements : Using the 3-D electronic integration approach Using very deep submicronic technology (65nm technology…) Using the HVCMOS …. We would like to thank you the fruitful IHEP-USTC collaboration during these development phases 295th FCPPL Workshop, Orsay-Saclay March 23, 2012Patrick Pangaud - CPPM-IN2P3-CNRS