Lecture 2 State-of-the art of CMOS Technology

The CMOS Transistor

The NMOS Transistor Cross Section Gate oxide n+ Source Drain p substrate Bulk (Body) Field-Oxide (SiO2) Polysilicon Gate L W Starting at the bottom of the design abstraction chart Gate Oxide – insulator NMOS – since carriers are electrons (n type carriers) M – metal; O – oxide; S – semiconductor Field oxide isolates one device from neighboring devices Base technology for the semester 0.25 micron transistor length L (drawn separation from source to drain) – 0.24 effective 1.0 micron transistor width W for minimum size transistor 2.5V supply voltage VDD 0.43 (-0.4) threshold voltage for NMOS (PMOS) devices so min W/L ratio in max for 250nm technology is 1/.24 View transistor as a switch with an infinite off-resistance and a finite on-resistance

Self-Aligned Gates NMOS Process Create thin oxide in the “active” regions, thick elsewhere Deposit polysilicon Etch thin oxide from active region (poly acts as a mask for the diffusion) Implant dopant Polysilicon gate is patterned before source and drain are created – thereby actually defining the precise location of the channel region and the locations of the source and drain regions. This allows for very precise positioning of the source and drain relative to the gate. Note that can’t completely stop lateral diffusion – accounts for difference between drawn transistor dimensions and actual ones

Photo-Lithographic Process optical mask oxidation photoresist photoresist coating removal (ashing) stepper exposure Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process spin, rinse, dry step

Patterning - Photolithography Oxidation deposits a thin layer of SiO2 over the complete wafer Wet Oxidation: water vapor (Furnace 900°C, 15 min, 40 nm) Si + 2H2O  SiO2 + 2H2 Dry oxidation: Pure O2 (Furnace 1000°C, 45 min, 40 nm) Si + O2  SiO2 insulation layer and also forms transistor gates. SiO2 SiO2 Same sequence patterns the complete surface of the wafer. Hence it is a very parallel process transferring hundreds of millions of patterns to the wafer surface simultaneously making cheap manufacturing of complex circuits possible. 1 – deposit thin layer of SiO2 by exposing it to a mixture of high-purity oxygen and hydrogen at 1000C 2 – light-sensitive polymer evenly applied while spinning the wafer to a thickness of 1 micron; polymers cross-link when exposed to light making the affected region insoluble (negative PR) or original insoluable, soluable after exposure (positive PR). COST OF MASKS IS INCREASING QUITE RAPIDLY WITH SCALING OF TECHNOLOGY – A REDUCTION OF MASKS IS OF HIGH PRIORITY! 3 – glass mask containing patter brought in close proximity to the wafer. Mask is transparent in regions we want to process and opaque elsewhere (positive PR). Combination exposed to UV light. Where mask is transparent, photoresist becomes soluable. Dimensions of features is approaching the wavelength of optical light sources (we’re good up to 0.1 micron). Will eventually move to X-ray or electron-beam (much less cost effective). 4 – Exposed photoresist is removed in a acid or base wash, then wafer is “soft-baked” to harden remaining PR 5 – Exposed material (SiO2) is removed via acid, base, and caustic solution wash. 6 – SRD – number of dust particles per cubic foot of air in clean room ranges between 1 and 10 8 – high-temperature plasma is used to selectively remove the remaining photoresist

Patterning - Photolithography 2. Photoresist coating: a light-sensitive polymer is evenly applied while spinning the wafer to a thickness of approximately 1 µm. -ve Photoresist: Originally soluble in organic solvent, but insoluble after exposure to UV light. +ve Photoresist: Originally insoluble in organic solvent, but soluble after exposure to UV light. SiO2 PR Same sequence patterns the complete surface of the wafer. Hence it is a very parallel process transferring hundreds of millions of patterns to the wafer surface simultaneously making cheap manufacturing of complex circuits possible. 1 – deposit thin layer of SiO2 by exposing it to a mixture of high-purity oxygen and hydrogen at 1000C 2 – light-sensitive polymer evenly applied while spinning the wafer to a thickness of 1 micron; polymers cross-link when exposed to light making the affected region insoluble (negative PR) or original insoluable, soluable after exposure (positive PR). COST OF MASKS IS INCREASING QUITE RAPIDLY WITH SCALING OF TECHNOLOGY – A REDUCTION OF MASKS IS OF HIGH PRIORITY! 3 – glass mask containing patter brought in close proximity to the wafer. Mask is transparent in regions we want to process and opaque elsewhere (positive PR). Combination exposed to UV light. Where mask is transparent, photoresist becomes soluable. Dimensions of features is approaching the wavelength of optical light sources (we’re good up to 0.1 micron). Will eventually move to X-ray or electron-beam (much less cost effective). 4 – Exposed photoresist is removed in a acid or base wash, then wafer is “soft-baked” to harden remaining PR 5 – Exposed material (SiO2) is removed via acid, base, and caustic solution wash. 6 – SRD – number of dust particles per cubic foot of air in clean room ranges between 1 and 10 8 – high-temperature plasma is used to selectively remove the remaining photoresist

Patterning - Photolithography 3. Stepper exposure: a glass mask , containing the patterns that we want to transfer to the silicon opaque in the regions that we want to process, transparent in the others (assuming a negative Photoresist) Where the mask is transparent, the Photoresist becomes insoluble. UV light Same sequence patterns the complete surface of the wafer. Hence it is a very parallel process transferring hundreds of millions of patterns to the wafer surface simultaneously making cheap manufacturing of complex circuits possible. 1 – deposit thin layer of SiO2 by exposing it to a mixture of high-purity oxygen and hydrogen at 1000C 2 – light-sensitive polymer evenly applied while spinning the wafer to a thickness of 1 micron; polymers cross-link when exposed to light making the affected region insoluble (negative PR) or original insoluable, soluable after exposure (positive PR). COST OF MASKS IS INCREASING QUITE RAPIDLY WITH SCALING OF TECHNOLOGY – A REDUCTION OF MASKS IS OF HIGH PRIORITY! 3 – glass mask containing patter brought in close proximity to the wafer. Mask is transparent in regions we want to process and opaque elsewhere (positive PR). Combination exposed to UV light. Where mask is transparent, photoresist becomes soluable. Dimensions of features is approaching the wavelength of optical light sources (we’re good up to 0.1 micron). Will eventually move to X-ray or electron-beam (much less cost effective). 4 – Exposed photoresist is removed in a acid or base wash, then wafer is “soft-baked” to harden remaining PR 5 – Exposed material (SiO2) is removed via acid, base, and caustic solution wash. 6 – SRD – number of dust particles per cubic foot of air in clean room ranges between 1 and 10 8 – high-temperature plasma is used to selectively remove the remaining photoresist mask SiO2 PR

Patterning - Photolithography 4. Photoresist development and bake: the wafers are developed in either an acid or base solution to remove the non-exposed areas of Photoresist. wafer is “soft-baked” (after PR removal) at a low temperature to harden the remaining Photoresist. Same sequence patterns the complete surface of the wafer. Hence it is a very parallel process transferring hundreds of millions of patterns to the wafer surface simultaneously making cheap manufacturing of complex circuits possible. 1 – deposit thin layer of SiO2 by exposing it to a mixture of high-purity oxygen and hydrogen at 1000C 2 – light-sensitive polymer evenly applied while spinning the wafer to a thickness of 1 micron; polymers cross-link when exposed to light making the affected region insoluble (negative PR) or original insoluable, soluable after exposure (positive PR). COST OF MASKS IS INCREASING QUITE RAPIDLY WITH SCALING OF TECHNOLOGY – A REDUCTION OF MASKS IS OF HIGH PRIORITY! 3 – glass mask containing patter brought in close proximity to the wafer. Mask is transparent in regions we want to process and opaque elsewhere (positive PR). Combination exposed to UV light. Where mask is transparent, photoresist becomes soluable. Dimensions of features is approaching the wavelength of optical light sources (we’re good up to 0.1 micron). Will eventually move to X-ray or electron-beam (much less cost effective). 4 – Exposed photoresist is removed in a acid or base wash, then wafer is “soft-baked” to harden remaining PR 5 – Exposed material (SiO2) is removed via acid, base, and caustic solution wash. 6 – SRD – number of dust particles per cubic foot of air in clean room ranges between 1 and 10 8 – high-temperature plasma is used to selectively remove the remaining photoresist

Patterning - Photolithography 5. Acid etching: material is selectively removed from areas of the wafer that are not covered by Photoresist. accomplished through the use of many different types of acid, base and caustic solutions as a function of the material that is to be removed. Same sequence patterns the complete surface of the wafer. Hence it is a very parallel process transferring hundreds of millions of patterns to the wafer surface simultaneously making cheap manufacturing of complex circuits possible. 1 – deposit thin layer of SiO2 by exposing it to a mixture of high-purity oxygen and hydrogen at 1000C 2 – light-sensitive polymer evenly applied while spinning the wafer to a thickness of 1 micron; polymers cross-link when exposed to light making the affected region insoluble (negative PR) or original insoluable, soluable after exposure (positive PR). COST OF MASKS IS INCREASING QUITE RAPIDLY WITH SCALING OF TECHNOLOGY – A REDUCTION OF MASKS IS OF HIGH PRIORITY! 3 – glass mask containing patter brought in close proximity to the wafer. Mask is transparent in regions we want to process and opaque elsewhere (positive PR). Combination exposed to UV light. Where mask is transparent, photoresist becomes soluable. Dimensions of features is approaching the wavelength of optical light sources (we’re good up to 0.1 micron). Will eventually move to X-ray or electron-beam (much less cost effective). 4 – Exposed photoresist is removed in a acid or base wash, then wafer is “soft-baked” to harden remaining PR 5 – Exposed material (SiO2) is removed via acid, base, and caustic solution wash. 6 – SRD – number of dust particles per cubic foot of air in clean room ranges between 1 and 10 8 – high-temperature plasma is used to selectively remove the remaining photoresist

Patterning - Photolithography Spin, rinse, and dry: a special tool (called SRD) cleans the wafer with deionized water and dries it with nitrogen. smallest particle of dust or dirt can destroy the circuitry. processing steps are performed in ultra-clean rooms where the number of dust particles per cubic foot of air ranges between 1 and 10. the wafers must be constantly cleaned to avoid contamination, and to remove the left-over of the previous process steps. Same sequence patterns the complete surface of the wafer. Hence it is a very parallel process transferring hundreds of millions of patterns to the wafer surface simultaneously making cheap manufacturing of complex circuits possible. 1 – deposit thin layer of SiO2 by exposing it to a mixture of high-purity oxygen and hydrogen at 1000C 2 – light-sensitive polymer evenly applied while spinning the wafer to a thickness of 1 micron; polymers cross-link when exposed to light making the affected region insoluble (negative PR) or original insoluable, soluable after exposure (positive PR). COST OF MASKS IS INCREASING QUITE RAPIDLY WITH SCALING OF TECHNOLOGY – A REDUCTION OF MASKS IS OF HIGH PRIORITY! 3 – glass mask containing patter brought in close proximity to the wafer. Mask is transparent in regions we want to process and opaque elsewhere (positive PR). Combination exposed to UV light. Where mask is transparent, photoresist becomes soluable. Dimensions of features is approaching the wavelength of optical light sources (we’re good up to 0.1 micron). Will eventually move to X-ray or electron-beam (much less cost effective). 4 – Exposed photoresist is removed in a acid or base wash, then wafer is “soft-baked” to harden remaining PR 5 – Exposed material (SiO2) is removed via acid, base, and caustic solution wash. 6 – SRD – number of dust particles per cubic foot of air in clean room ranges between 1 and 10 8 – high-temperature plasma is used to selectively remove the remaining photoresist

Patterning - Photolithography 7. Various Process step: the exposed area can now be subjected to a wide range of process steps Diffusion or Ion implantation Plasma etching Metal deposition Same sequence patterns the complete surface of the wafer. Hence it is a very parallel process transferring hundreds of millions of patterns to the wafer surface simultaneously making cheap manufacturing of complex circuits possible. 1 – deposit thin layer of SiO2 by exposing it to a mixture of high-purity oxygen and hydrogen at 1000C 2 – light-sensitive polymer evenly applied while spinning the wafer to a thickness of 1 micron; polymers cross-link when exposed to light making the affected region insoluble (negative PR) or original insoluable, soluable after exposure (positive PR). COST OF MASKS IS INCREASING QUITE RAPIDLY WITH SCALING OF TECHNOLOGY – A REDUCTION OF MASKS IS OF HIGH PRIORITY! 3 – glass mask containing patter brought in close proximity to the wafer. Mask is transparent in regions we want to process and opaque elsewhere (positive PR). Combination exposed to UV light. Where mask is transparent, photoresist becomes soluable. Dimensions of features is approaching the wavelength of optical light sources (we’re good up to 0.1 micron). Will eventually move to X-ray or electron-beam (much less cost effective). 4 – Exposed photoresist is removed in a acid or base wash, then wafer is “soft-baked” to harden remaining PR 5 – Exposed material (SiO2) is removed via acid, base, and caustic solution wash. 6 – SRD – number of dust particles per cubic foot of air in clean room ranges between 1 and 10 8 – high-temperature plasma is used to selectively remove the remaining photoresist

Patterning - Photolithography Photoresist Removal (ashing): a high-temperature plasma ( mix of chemical materials) is used to selectively remove the remaining Photoresist without damaging device layers. Same sequence patterns the complete surface of the wafer. Hence it is a very parallel process transferring hundreds of millions of patterns to the wafer surface simultaneously making cheap manufacturing of complex circuits possible. 1 – deposit thin layer of SiO2 by exposing it to a mixture of high-purity oxygen and hydrogen at 1000C 2 – light-sensitive polymer evenly applied while spinning the wafer to a thickness of 1 micron; polymers cross-link when exposed to light making the affected region insoluble (negative PR) or original insoluable, soluable after exposure (positive PR). COST OF MASKS IS INCREASING QUITE RAPIDLY WITH SCALING OF TECHNOLOGY – A REDUCTION OF MASKS IS OF HIGH PRIORITY! 3 – glass mask containing patter brought in close proximity to the wafer. Mask is transparent in regions we want to process and opaque elsewhere (positive PR). Combination exposed to UV light. Where mask is transparent, photoresist becomes soluable. Dimensions of features is approaching the wavelength of optical light sources (we’re good up to 0.1 micron). Will eventually move to X-ray or electron-beam (much less cost effective). 4 – Exposed photoresist is removed in a acid or base wash, then wafer is “soft-baked” to harden remaining PR 5 – Exposed material (SiO2) is removed via acid, base, and caustic solution wash. 6 – SRD – number of dust particles per cubic foot of air in clean room ranges between 1 and 10 8 – high-temperature plasma is used to selectively remove the remaining photoresist

Example: Patterning of SiO2 Chemical or plasma etch Si-substrate Hardened resist SiO 2 (a) Silicon base material Si-substrate Photoresist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO Si-substrate 2 (b) After oxidation and deposition Hardened resist of negative photoresist SiO 2 Si-substrate UV-light Patterned (e) After etching optical mask Exposed resist SiO 2 Si-substrate Si-substrate (f) Final result after removal of resist (c) Stepper exposure

Process steps Diffusion or Ion implantation: Diffusion implantation: the wafers are placed in a quartz tube embedded in a heated furnace. A gas containing the dopant is introduced in the tube. The high temperatures of the furnace, typically 900 to 1100 °C, cause the dopants to diffuse into the exposed surface both vertically and horizontally. Not accurate (difference in dopant concentration through the material) Needed for well, source and drain regions, doping of polysilicon, adjustment of thresholds Diffusion – wafer placed in quartz tube embedded in a furnace (900 to 1100 C). Gas containing dopant is introduced in the tub. Dopands diffused into the exposed surface both vertically and horizontally. Final dopant concentration is highest at surface and decreases in a gaussian profile deeper in the material Ion implantation – Dopants are introduced as ions into the material by sweeping a beam of purified ions over the surface - acceleration determines how deep ions will penetrate and the beam current and exposure time determine dosage. Independent control of depth and dosage – ion implantation has largely displaced diffusion. However, has a side effect of causing lattice damage to substrate, so usually follow with an annealing step (wafer heated to 1000C for 15 to 30 minutes and allowed to cool slowly). Heating vibrates atoms and allows the bonds to reform.

Process steps Diffusion or Ion implantation: Ion implantation: dopants are introduced as ions into the material. The ion implantation system directs and sweeps a beam of purified ions over the semiconductor surface. The acceleration of the ions determines how deep they will penetrate the material, the beam current and the exposure time determine the dosage. It controls depth and dosage, therefore it displaced diffusion implantation in modern semiconductor manufacturing. Needed for well, source and drain regions, doping of polysilicon, adjustment of thresholds Diffusion – wafer placed in quartz tube embedded in a furnace (900 to 1100 C). Gas containing dopant is introduced in the tub. Dopands diffused into the exposed surface both vertically and horizontally. Final dopant concentration is highest at surface and decreases in a gaussian profile deeper in the material Ion implantation – Dopants are introduced as ions into the material by sweeping a beam of purified ions over the surface - acceleration determines how deep ions will penetrate and the beam current and exposure time determine dosage. Independent control of depth and dosage – ion implantation has largely displaced diffusion. However, has a side effect of causing lattice damage to substrate, so usually follow with an annealing step (wafer heated to 1000C for 15 to 30 minutes and allowed to cool slowly). Heating vibrates atoms and allows the bonds to reform.

2) Deposition: Process steps Oxidation SiO2 (insulating material) CVD (Chemical Vapor Deposition) of (Si3N4) (buffer layer, to protect the field oxide ) chemical deposition (polysilicon) (flows silane gas over the heated wafer coated with SiO2 at a temperature of approximately 650°C sputtering (Al) (The aluminum is evaporated in a vacuum, with the heat for the evaporation delivered by electron-beam or ion-beam bombarding. ) Needed for well, source and drain regions, doping of polysilicon, adjustment of thresholds Diffusion – wafer placed in quartz tube embedded in a furnace (900 to 1100 C). Gas containing dopant is introduced in the tub. Dopands diffused into the exposed surface both vertically and horizontally. Final dopant concentration is highest at surface and decreases in a gaussian profile deeper in the material Ion implantation – Dopants are introduced as ions into the material by sweeping a beam of purified ions over the surface - acceleration determines how deep ions will penetrate and the beam current and exposure time determine dosage. Independent control of depth and dosage – ion implantation has largely displaced diffusion. However, has a side effect of causing lattice damage to substrate, so usually follow with an annealing step (wafer heated to 1000C for 15 to 30 minutes and allowed to cool slowly). Heating vibrates atoms and allows the bonds to reform.

3) Etching: Process steps Wet Etching: Dry (or Plasma) Etching: etching is used to selectively form patterns such as Via and contact holes. Wet Etching: (makes use of acid or basic solutions, such as hydrofluoric acid to etch SiO2) Dry (or Plasma) Etching: - A wafer is placed into the etch tool's processing chamber and given a negative electrical charge. - The chamber is heated to 100°C and brought to a vacuum level of 7.5 Pa, then filled with a positively charged plasma (usually a mix of nitrogen, chlorine and boron trichloride). - The opposing electrical charges cause the rapidly moving plasma molecules to align themselves in a vertical direction, forming a microscopic chemical and physical “sandblasting” action which removes the exposed material. - Plasma etching has the advantage of offering a well-defined directionality to the etching action, creating patterns with sharp vertical contours. Needed for well, source and drain regions, doping of polysilicon, adjustment of thresholds Diffusion – wafer placed in quartz tube embedded in a furnace (900 to 1100 C). Gas containing dopant is introduced in the tub. Dopands diffused into the exposed surface both vertically and horizontally. Final dopant concentration is highest at surface and decreases in a gaussian profile deeper in the material Ion implantation – Dopants are introduced as ions into the material by sweeping a beam of purified ions over the surface - acceleration determines how deep ions will penetrate and the beam current and exposure time determine dosage. Independent control of depth and dosage – ion implantation has largely displaced diffusion. However, has a side effect of causing lattice damage to substrate, so usually follow with an annealing step (wafer heated to 1000C for 15 to 30 minutes and allowed to cool slowly). Heating vibrates atoms and allows the bonds to reform.

Process steps 4) Planarization: This process uses a slurry compound—a liquid carrier with a suspended abrasive component such as aluminum oxide or silica—to microscopically plane a device layer and to reduce the step heights. chemical-mechanical planarization (CMP) step is included before the deposition of an extra metal layer on top of the insulating SiO2 layer. Needed for well, source and drain regions, doping of polysilicon, adjustment of thresholds Diffusion – wafer placed in quartz tube embedded in a furnace (900 to 1100 C). Gas containing dopant is introduced in the tub. Dopands diffused into the exposed surface both vertically and horizontally. Final dopant concentration is highest at surface and decreases in a gaussian profile deeper in the material Ion implantation – Dopants are introduced as ions into the material by sweeping a beam of purified ions over the surface - acceleration determines how deep ions will penetrate and the beam current and exposure time determine dosage. Independent control of depth and dosage – ion implantation has largely displaced diffusion. However, has a side effect of causing lattice damage to substrate, so usually follow with an annealing step (wafer heated to 1000C for 15 to 30 minutes and allowed to cool slowly). Heating vibrates atoms and allows the bonds to reform.

CMOS Process

CMOS Process Layers Color Legend Representation Well (n) Green Active Area (n+) Green Select (n+) Green Well (p) Yellow Active Area (p+) Yellow Select (p+) Yellow Polysilicon Red Metal1 Blue Metal2 Magenta Contact or Via Black

Complete Simplified CMOS Inverter Process cut line p well n type substrate - p well/tub

P-Well Mask Creation in the N Type Substrate After p-well use implants to adjust VTn

Active Mask Creation (n+ and p+ Regions) (Continue) Grown thick oxide. Then use active mask to create thin oxide layers over the active areas – where we are going to place the transistors (source, gate, and drain areas)

Poly Silicon Mask Creation First used chemical deposition to deposit polysilicon on wafer. Note thin oxide area for gate oxide - critical (helps determine Vth) doe 0.25 micron technology -> 6.5 to 5.5 microns thick

P+ Mask Creation Followed by diffusion (ion implant) to build pfets source and drain areas

N+ Mask Creation (Continue) Followed by diffusion (ion implant) to build nfets source and drain areas

Contact Mask Creation After deposition of SiO2 insulator, then contact holes are etched (in this case to make contacts to source and drain regions)

Metal Mask Creation (Continue) 62 processing steps for a double/twin tub CMOS process!! tanqueray.eecs.berkeley.edu/~ehab/inv.html

A Modern CMOS Process Twin-Tub or Dual-Well Trench gate-oxide TiSi AlCu 2 SiO 2 Tungsten p-well n-well SiO 2 n+ p- epi p+ p+ Dual-Well Trench-Isolated CMOS Process

Procedure of Modern CMOS Process Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers One full photolithography sequence per layer (mask)

Modern CMOS Process Walk-Through + p-epi Base material: p+ substrate with p-epi layer p + p-epi SiO 2 3 Si N 4 After deposition of gate-oxide and sacrifical nitride (acts as a buffer layer) These would be best to convert to color – but I don’t have the energy!! p + After plasma etch of insulating trenches using the inverse of the active area mask

CMOS Process Walk-Through (continue) SiO 2 After trench filling, CMP planarization, and removal of sacrificial nitride After n-well and VTp adjust implants n After p-well and VTn adjust implants p

3.5 CMOS Process Walk-Through (continue) After polysilicon deposition and etch poly(silicon) After n+ source/drain and p+ source/drain implants. These steps also dope the polysilicon. p + n After deposition of SiO2 insulator and contact hole etch SiO 2

CMOS Process Walk-Through (continue) After deposition and patterning of first Al layer. Al After deposition of SiO2 insulator, etching of via’s, deposition and patterning of second layer of Al. Al SiO 2

Bonding Techniques

Tape-Automated Bonding (TAB)

Flip-Chip Bonding

Package-to-Board Interconnect