IC Design Research Laboratory 1 Design StatusMay 2014 Custom Chip For Use With Silicon Strip Detectors IC Design Research Laboratory Department of Electrical and Computer Engineering Southern Illinois University Edwardsville, IL, Raghu Teja Singamaneni

IC Design Research Laboratory Si Strip Detector 2

IC Design Research Laboratory Energy Branch Block Diagram

IC Design Research Laboratory Layout of HINP4 4

IC Design Research Laboratory A BIG THANK YOU goes out to all of the students who worked on the chip over the past 4 years !!!! 5 Raghu Singamaneni Srikanth Thota Smita Patel Junaid Ali Mir Areeb Sam Dunham Uttam Bavaria Geetha Ravi Ataisi Eneyo

IC Design Research Laboratory Packaged Parts 6

IC Design Research Laboratory HINP Chip and Mother Board 7

IC Design Research Laboratory 8 High Gain Mode Shaper Output for Electron Collection with Energy level: 10MeV : (Cdet : 75pF) Settling Time:5 µs NOTE the excellent return to baseline characteristics when the dynamic reset circuit is used. Peaking time is 1.5 usec. High Gain Mode Shaper Output for Hole Collection with Energy level: 10MeV: (Cdet : 75pF) NOTE that it takes much longer to return to baseline because of the real feedback resistor. Current shaper has no way to cancel the pole which is introduced by the feedback resistor. The novel reset circuit used above cannot be used because of the poor 1/f noise performance of NFETs in this process. Peaking time is 1.5 usec. Settling Time: 50µS

IC Design Research Laboratory Hole Collection 9

IC Design Research Laboratory Electron Collection 10

IC Design Research Laboratory 11 Energy Resolution 11

IC Design Research Laboratory Linearity Plots (Electron Collection) 12

IC Design Research Laboratory Linearity Plots (Hole Collection) 13

IC Design Research Laboratory CFD Block Diagram CSA signal comes from first op amp in the slow shaper of the high gain branch in energy branch slide. Digital delay block in zero-cross leg compensates for delay through x10 amplifier. Timing portion of chip also needed to be improved so as to allow for triggering to a much lower level.

IC Design Research Laboratory Multiplicity 15

IC Design Research Laboratory Minimum Trigger Level of CFD Minimum trigger level set so that threshold is 6 times the RMS noise level at input to leading-edge circuit and LE signal must fire before ZC signal. Preliminary tests indicate that things are looking good!!!!

IC Design Research Laboratory CFD Walk Performance (Electron Collection)

IC Design Research Laboratory CFD Walk Performance (Hole Collection)

IC Design Research Laboratory 19 THANK YOU! …QUESTIONS?????