1 IRAM Vision Microprocessor & DRAM on a single chip: –on-chip memory latency 5-10X, bandwidth X –improve energy efficiency 2X-4X (no off-chip bus) –serial I/O 5-10X v. buses –smaller board area/volume –adjustable memory size/width DRAMDRAM fabfab Proc Bus DRAM $$ Proc L2$ LogicLogic fabfab Bus DRAM I/O Bus BusBus

2 VIRAM-1 Specs/Goals Technology micron, 5-6 metal layers, fast xtor Memory16-32 MB Die size≈ mm 2 Vector pipes/lanes4 64-bit (or 8 32-bit or bit) TargetLow PowerHigh Performance Serial I/O4 1 Gbit/s8 2 Gbit/s Power university ≈ volt logic≈ volt logic Clock univers. 200scalar/200vector MHz300sc/300vector MHz Perf university 1.6 GFLOPS GOPS GFLOPS GOPS 16 Power industry ≈ volt logic≈ volt logic Clock industry 400scalar/400vector MHz600s/600v MHz Perf industry 3.2 GFLOPS GOPS 16 4 GFLOPS GOPS 16

3 IRAM Update 2 test chips: serial lines (MOSIS) + Embedded DRAM/Crossbar (LG Semicon) Simulator/Architecture Manual Completed Initial Vector Compiler (“VIC”) Completed Partner for scalar processor (Sandcraft/MIPS) LG delays, prospects => stick to plan to re-evaluate options for IRAM prototype –Foundary: TSMC, UMC –DRAM companies: IBM, Micron, NEC, Toshiba Applications: FFT, segmentation,...

4 IRAM App: ISTORE (“Intelligent Storage”) 1 IRAM/DRAM + crossbar switch + fast serial link v. conventional SMP Move function to data v. data to CPU $$ Proc L2$ Conventional CPU Bus IRAMIRAM IRAMIRAM IRAMIRAM IRAMIRAM I/O Bus BusBus cross bar …

5 Another Vision of ISTORE 1 IRAM/disk + xbar + fast serial link v. conventional SMP, cluster Network latency = f(SW overhead), not link distance Move function to data v. data to CPU (scan, sort, join,...) Cost/performace, more scalable … cross bar … … … IRAM … … … … … cross bar CPU/Memory

6 ISTORE Update Build prototypes to gain experience, develop software before IRAM chips arrive –Replace with IRAM chips once available ISTORE-0: 2 Sandcraft Development boards + Fast Ethernet + Real-time OS (VxWorks/QNX) ISTORE-1: “Intelligent SIMM” module based on Mitsubishi M32RXD (DRAM interface+CPU)

7 IRAM/ISTORE Schedule IRAMISTORE/OSCompiler

IRAM/ISTORE Presentations –MicroDesign Resources Dinner Meeting, 1/8/98 –Embedded Memory Workshop, Japan, 3/15/98 –Stanford Computer Science Colloquim, 5/6/98 –University of Virginia Distinguished Lecture, 5/19/98 –SIGMOD98 Keynote Address, 6/3/98 Articles –“New Processor Paradigm: V-IRAM”, Microprocessor Report, 3/9/98, –“A perfect match.” New Scientist, 4/18/98, –"Professor's Idea for Speedy Chip Could Be More Than Academic," Wall Street Journal, 8/28/98, B1, B4.