The SuperB Silicon Vertex Tracker Abstract : The SuperB project aims to build an asymmetric e+ - e- collider capable of reaching a luminosity exceeding cm -2 s -1 at the energy of the Y(4S) resonance. With such luminosity flavour physics can probe in a unique manner the structure of the New Physics beyond the Standard Model, making the SuperB scientific program complementary to the physics goals of the LHC. Comparing to current B-Factories, the reduced beam energy asymmetry (7GeVx4GeV) of the new accelerator requires an improved vertex resolution that could be achieved with a vertex detector design based on the current BaBar SVT with the addition of an innermost Layer0 very close to the impact point, with high granularity, low material budget and capable to sustain a background rate of several MHz/cm2. The reduced beam energy asymmetry of the SuperB machine (7x4 GeV) requires an improved vertex resolution to achieve performance similar to present B-Factories on time dependent measurements. The SuperB Silicon Vertex Tracker Target perfomance (BaBar) can be achieved with a vertex detector design based on the current BaBar Silicon Vertex Tracker + an innermost Layer0 very close to the IP (R~ 1.5 cm) with low material budget (~ 1% X0) BaBar SVT 5 Layers of double-sided Si strip sensor Low-mass design. ( Pt < 2.7 GeV/c 2 for B daughters) Stand-alone tracking for slow particles. 97% reconstruction efficiency Hit resolution ~15mm at normal incidence BaBar SVT 5 Layers of double-sided Si strip sensor Low-mass design. ( Pt < 2.7 GeV/c 2 for B daughters) Stand-alone tracking for slow particles. 97% reconstruction efficiency Hit resolution ~15mm at normal incidence  t resolution (ps) MAPS (2 layers) Hybrid Pixels (single layer) B   decay mode,  =0.28, beam pipe X/X0=0.42%, hit resolution =10  m Fast Simulation Pixel module integration for Layer 0 Pinwheel Layer0 Layout Layer0 options for SuperB CMOS MAPS: new & challenging technology, very promising  sensor & readout in 50  m thick chip! Extensive R&D (SLIM5-Collaboration) on Deep N-well devices 50x50  m 2 with in pixel sparsification. – Fast readout architecture implemented Specs: Effi>95% with 100 MHit/cm2 on full Layer0 matrix size – CMOS MAPS matrix with 4k pixels successfully tested with beams. Striplets : thin double sided silicon sensor with short strips mature technology, less robust against background occupancy. Thin pixels with Vertical Integration: Reduction of material and improved performance possible with the technology leap offered by vertical integration. DNW MAPS with 2 tiers (Chartered/Tezzaron 130 nm) submitted in April Hybrid Pixels viable option  baseline for TDR Reduction in the front-end pitch to 50x50  m 2 with data push readout architecture developed for CMOS DNW MAPS. – First prototype FE chip submitted by the end of Different Layer0 options under study for TDR (end of 2010) Layer 0 specs: > 5MHz/cm2, 1MRad/yr, 1%X0 Lower material & improved performance Sensor Digital tier Analog tier Wafer bonding & electrical interconn. ST Microelectronics 130 nm Layer0 R&D Recent Results Successfully tested two options for Layer0 CMOS MAPS matrix with fast readout architecture (4096 pixels, 50x50  m pitch, sparsification and timestamp) – Hit efficiency up to 92% with room for improvement – Intrisinc resolution ~ 14  m compatible with digital readout. Thin striplets module - FSSR2 readout chips – S/N=25 (thickness 200  m), Efficiency > 98% First demostration of LVL1 capability with silicon tracker information sent to Associative Memories More details: M. Villa - talk, L. Vitale - poster Light support structure with integrated cooling needed for pixel module (P= 2W/cm 2 ) Carbon Fiber support with integrated microchannels with coolant fluid developed: – Total support/cooling thickness ~ 0.3 % X 0 First thermo-hydraulic measurements on prototypes in good agreement with simulation. Thermofluidodynamics Lab ready in Pisa (More details: F. Bosi’s poster) Carbon Fiber Support with microchannels 12.8 mm 0.7 mm 0.5 MIP SuperB Low currents (2A): – Beam-gas are not a problem (similar to BaBar) – SR fan can be shielded High luminosity  dominated by QED cross section Rate (Mhz/cm2) IR design Rate reduced to ~ 100 SVT location with present IR design and proper shielding to prevent the produced shower from reaching the detector Radius (cm) Rate reduced to 5 MHz/cm2 at first SVT layer since e+/e- have low energy and loop in the 1.5T B field.  The BaBar SVT technology is adequate for R > 3cm Layer0: Backg. track rate 5MHz/cm2, TID 1MRad/yr MAPS Hit Efficiency vs threshold 90 Sr electrons APSEL3T1 M2 Landau mV S/N=23 Cluster signal (mV) Noise events properly normalized APSEL4D chip bonded to the chip carrier Different options under study on interfaces for multichip pixel module – BUS needs: low material (Al based), many lines, high frequency (~160 MHz) – HDI - power/signal input and data output link On detector High rad area Off detector low rad area Counting room Std electronics EDRO board (SLIM5) with large FPGA, memory (i.e. flexible) and optical links (2.5 Gbit/s) as interface between FE chips and SuperB trigger and DAQ ROM optical/copper Link Memory buffers And L1 logic EDRO Buffers and line drivers ~50 mm Half Module Layer0 module rates: 20 Gbit/s full rate (FE data push), 3 Gbit/s triggered rate Giuliana Rizzo* Universita’ degli Studi and INFN Pisa, Italy on behalf of the SuperB Group 11th Pisa Meeting on Advanced Detectors – May cm 30 cm 20 cm Layer0 old beam pipenew beam pipe