RTL Simulator for VChip 1999/11/11 이재곤

RTL Simulator for VChip  현재 상황 Compiled-code 로 변환 중  VBS 의 내장된 obj 파일을 이용하려 하였으나 제 대로 구현되어 있지 않음  Obj 파일 : 각 module 의 definition 을 기억

Schedule 11/211/311/4 계획 진행 Compiled-code 변환 완성 H/W interface

The Incredible Shirinking trnasistor 이 재 곤

Introduction  The steady down-scaling of CMOS device has been the main stimulus to the growth of microelectronics and computer industry Down-scaling Packing density Circuit Speed Lower Power

Problems with Scaling  The smallest features in a CMOS transistor is approaching atomic dimensions  Off-state leakage current is rising  Parastic components are getting bigger How much longer can CMOS scaling continue?

Trend  CMOS with shorter channel length  Higher Performance Example(2003~2006)  0.10~0.13um lithography  Minimum channel length of 0.05um  Operating Frequency > 100GHz

Power  Scaling down  Channel length scales down  Power supply voltage must be reduced  Active power reduced (propotional to Vdd 2 )  Threshold voltage scales down?  No. Subthreshold behavior follows directly from thermodynamics and is independent of power supply voltage

Power and Performance  CMOS power and performance are largely governed by the choices of power supply and threshold voltage CMOS performance is a function of the ratio of the threshold voltage to power supply voltage  Performance comes at the cost of higher active power or higher stand by power or both

Power and Performance

Power and Performance (solution)  Devices with different threshold voltges on the same chip Low threshold devices used in critical logic paths for speed High threshold devices used every-where else for low standby power  Sleep mode  Dynamic threshold devices The threshold voltage is controlled by a backgate biase voltage in bulk silicon

Gate Oxide Thickness  Gate oxide thickness is reduced in proportion to channel length  In 0.10~0.13um lithography, an oxide thickness of 1~2 nm is needed  A nanometer or so of oxide consists of only a few layers of atoms and is approaching funcamental limits

Gate Oxide Thickness (Limits)  Tunneling Gate leakage current that increases exponentially as the oxide thickness is scaled down Standby power increases 1.5~2nm limit for the gate oxide thickness  Inversion layer quantization effect  Ceter of mass of the inversioncharge distribution is farther away from the surface  The effect is equivalent to adding about 0.4nm to the gate oxide thickness when the MOSFET is on

Gate Oxide Thickness (Limits) 0.4nm

Channel profile design  Various vertically nonuniform doping profile have been empolyed in previous CMOS generations  Some lateral nonuniformity, called a halo, was introduced below 0.20um channel length  In the 0.10~0.13um lithography generation, an optimally tailored profile htat is both vertically and laterally nonuniform (super halo) is needed

Channel profile design

Fluctuating number of discrete dopant atoms  Fluctuating number of discrete dopant atoms in the smal gate depletion region  In the 0.10~0.13um generation, that region will contain only a couple of hundred of dopant atoms  Their sparsity is the source of threshold voltage uncertainty

Sharp source-drain junctions  Source and drain junctions with truly abrupt lateral doping profile  The abruptness needed is on the scale of a fraction of the channel length

Summary  Problems with scaling Power and Performance Gate oxide thickness Channel progile design Fluctuating number of dopant atoms Sharp source-drain junctions