1 Asynchronous Sequential Logic For most figures:

2 We know… don’t we?  We have learned how to analyze and design circuits with memory, don’t we?  We have designed really complicated circuits and can do so for any problem, right?  How about taking a look at our lovely latch circuit again?

3 Asynchronous Sequential Circuits  No clock pulses  Change of an internal state occurs when there is a change in the inputs.  More difficult to design/analyze than synchronous sequential circuits.  Useful in cases where speed is important.  More economical to use.  Combinational circuits with feedback loops (connected through delayed lines).  Secondary variables: input end of the feedback loops., e.g. y 1, y 2,… y k.

4 Example One input: x Two feedback loops Two excitation variables: – Y 1 and Y 2 Two secondary variables: – y 1 and y 2

5 Transition table Y 1 = xy 1 + x’y 2 Y 2 = xy 1 ’ + x’y 2 The input (x) is also part of the state Stable states are the circled ones where – Y 1 = y 1 and Y 2 = y 2 Y 1 Y 2

6 Understanding the transition table Four stable states: – y 1 y 2 x = {000,011,110,101} If y 1 y 2 x = 000 and x: 0  1 – Then Y 1 Y 2 x = 011

7 Procedure for analysis Determine all feedback loops Assign Y i 's (excitation variables), y i 's (the secondary variables) Derive the Boolean functions of all Y i 's Plot each Y function in a map Construct the state table Circle the stable states

8 Flow Table A flow table is a state transition table with its internal state being symbolized with letters (a) is called a primitive flow table since it has only one stable state in each row output

9 Designing an Async. Seq. Circuit Assign – a = 0 – b = 1

10 Race Conditions Race conditions occur when two or more state variables are supposed to change simultaneously due to a change in the input. For instance: – From y 1 y 2 =00 to y 1 y 2 = 11 – Three possible transitions: 00   10   01  11 Critical vs non-critical race conditions

11 Non-critical races Three possible transitions: – 00  11 – 00  10  11 – 00  01  11 If all possible transitions lead us to the same final state, then it is a non- critical race.

12 Critical races Three possible transitions: – 00  11 – 00  10  11 – 00  01  11 If different transitions lead to different final states, then it is a critical race.

13 Cycles Cycle: a unique sequence of unstable states that the circuit goes.

14 Unstability Y = (x 1 y)’x 2 = x 1 ’x 2 + x 2 y’ If x 1 x 2 y = 111  Y = 0 If x 1 x 2 y = 110  Y = 1 Oscillation between 1 and 0. Y will be a square wave.

15 SR latch - revisited Forbidden input: 11

16 Quizz Write your name and ID Derive the transition table of the following circuit

17 Asynchronous sequential circuits No clock pulses Change of an internal state occurs when there is a change in the inputs. More difficult to design/analyze than synchronous sequential circuits. Useful in cases where speed is important. More economical to use. Combinational circuits with feedback loops (connected through delayed lines). Secondary variables: input end of the feedback loops., e.g. Y1, y2,… yk. Previously!

18 Transition table Y1 = xy1 + x’y2 Y2 = xy1’ + x’y2 The input (x) is also part of the state Stable states are the circled ones where – Y1 = y1 and Y2 = y2 Y 1 Y 2 Previously!

19 Procedure for analysis Determine all feedback loops Assign Y i 's (excitation variables), y i 's (the secondary variables) Derive the Boolean functions of all Y i 's Plot each Y function in a map Construct the state table Circle the stable states Previously!

20 Flow table A flow table is a state transition table with its internal state being symbolized with letters (a) is called a primitive flow table since it has only one stable state in each row output Previously!

21 Designing an asynch. seq. ckt. Assign – a = 0 – b = 1 Previously!

22 Race conditions Race conditions occur when two or more state variables are supposed to change simultaneously due to a change in the input. For instance: – From y1y2=00 to y1y2 = 11 – Three possible transitions: 00   10   01  11 Critical vs non-critical race conditions Previously!

23 Critical races Three possible transitions: – 00  11 – 00  10  11 – 00  01  11 If different transitions lead to different final states, then it is a critical race. Previously!

24 Cycles Cycle: a unique sequence of unstable states that the circuit goes. Previously!

25 Analysis example

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27 Design with a latch WRONG! How were we designing in Sequential Logic?

28 Debounce circuit Unconnected S or R is pulled to 1. When connected, they are pulled down to 0. Switch at A: S=0 and R=1; Q = 1, Q’=0 Switch at B: S = 1 and R = 0; Q=0, Q’=1 Bounce back from B (not touching back to A): S =1 and R=1; Q=0, Q’=1

29 Design Procedure Gated latch with two inputs G and D. If G=1, then Q (latch output) should follow D. When G becomes 0, then the value of D at the time of the transition from G=1 to G=0 is retained at Q; i.e., once G becomes 0, the value of D does not change Q. InputsOutput StateDGQComments a010D=Q because G=1 b111 c000After state a or d d100After state c e101After state b or f f001After state e Let us start by giving a state to each row.

30 InputsOutput StateDGQComments a010D=Q because G=1 b111 c000After state a or d d100After state c e101After state b or f f001After state e Primitive flow table formation Step 1: Stable states, and outputs are inserted. Since we allow only one of DG to change, put ‘-’ to where they both change.

31 Primitive flow table formation-2 Step 1: Stable states, and outputs are inserted. Step 2: Unstable states are determined. Outputs at these unstable states don’t matter. Use ‘-’ to indicate this.

32 Reduction of the flow table

33 Set a=0 and b=1 Transition table

34 Gated latch logic

35 Gated latch with SR latch

36 Assigning output to unstable states Set the output of the transient state to 0 if the start and finish states have the output 0. Set the output of the transient state to 1 if the start and finish states have the output 1. Set the output of the transient state to ‘-’ if the start and finish states have different outputs.

37 Design Procedure Gated latch with two inputs G and D. If G=1, then Q (latch output) should follow D. When G becomes 0, then the value of D at the time of the transition from G=1 to G=0 is retained at Q; i.e., once G becomes 0, the value of D does not change Q. InputsOutput StateDGQComments a010D=Q because G=1 b111 c000After state a or d d100After state c e101After state b or f f001After state e Let us start by giving a state to each row. Previously!

38 InputsOutput StateDGQComments a010D=Q because G=1 b111 c000After state a or d d100After state c e101After state b or f f001After state e Primitive flow table formation Step 1: Stable states, and outputs are inserted. Since we allow only one of DG to change, put ‘-’ to where they both change. Previously!

39 Primitive flow table formation-2 Step 1: Stable states, and outputs are inserted. Step 2: Unstable states are determined. Outputs at these unstable states don’t matter. Use ‘-’ to indicate this.

40 Reduction of the flow table Previously!

41 Set a=0 and b=1 Transition table Previously!

42 Gated latch logic Previously!

43 Gated latch with SR latch Previously!

44 Assigning output to unstable states Set the output of the transient state to 0 if the start and finish states have the output 0. Set the output of the transient state to 1 if the start and finish states have the output 1. Set the output of the transient state to ‘-’ if the start and finish states have different outputs.

45 A formal procedure for reducing flow table In (a,b), x=0 -> next states: (c,d) x=1 -> next states: (a,b) In (c,d), x=0 -> next states: (a,b) x=1 -> next state: d Any Equivalent States? If c=d, then we can say a=b. In other words, (a,b) implies (c,d).

46 A formal procedure for reducing flow table  Place a X for all pairs of states whose outputs differ.  Fill in the remaining cells with values of implied states.  For each confirmed implication, put a tick.

47 Implication table from the flow table What happens if the circuit is not completely specified? Compatible states: two incompletely specified states that can be combined (i.e., there is no conflict! )

48 Merger Diagram for Finding Maximal Compatibles Links are drawn between compatible states. An n-state compatible is represented by an n-sided polygon with all its diagonals connected.

How to Merge using the Merger Diagram? The resulting set of compatibles need to be: Covering: Contains all initial states. Closed: Contains all the implied states. The closed & covering set of compatibles determine the reduced flow table. So, what is the subset of (a,b), (a,c,d), (b,e,f) that satisfy coverage and closedness? For coverage, (a,c,d) and (b,e,f) are sufficient. Do (a,c,d) and (b,e,f) satisfy closedness? Are the implied states of (a,c), (a,d), (c,d), (b,e), (b,e), (b,f) included in the selected set?

50 Another Example for Merger Diagram

Quizzzz… 1. Derive the implication table for the following transition table. 2. Draw the merger diagram and determine the set of maximal compatibles. 3. Determine the minimum set of maximal compatibles and draw the reduced transition table. 51

52 Quizzzz Derive the transition table of the following circuit. Draw the implication table and show whether any reduction is possible.

53 Assigning Binary Numbers to States Goal: Assign the numbers so that no critical races occur! Change only one variable during a transition!!

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60 Hazards A hazard is a condition in which a change in a single variable produces a momentary change in output when no change should occur. All inputs are 1 at the beginning. When x2 becomes 0, due to delay caused by the NOT gate, Y may temporarily become 0.

61 Types of Hazards

62 Removing Hazards Hazars are produced when changing from one term to another! This causes a problem because during the transition, neither of the terms might be 1. So, make redundant terms/groups so that the new terms make sure that the transition is covered.

63 The Circuit After Removing the Hazard

64 Another way to avoid hazards Implement the circuit with SR latches!!! Why would this remove hazards?

65 Implementation with SR latches to avoid hazards

66 Essential Hazards Due to delays, feedback loops might produce hazards. These hazards cannot be corrected by adding gates/terms. They can be avoided only by adjusting the delays in the feedback loops according to the delays in the input signals.

Quiz the last of the Asyncronous Logic part 67 Check whether the following circuit has a hazard. If it does, remove the hazard by both a) adding redundant terms to the Y function, b) implementing the circuit with SR-latches.

68 Example Design

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