CSCI2510 Tutorial 5 Introduction to Cache Zong Wen

Slides:



Advertisements
Similar presentations
Topics covered: Memory subsystem CSE243: Introduction to Computer Architecture and Hardware/Software Interface.
Advertisements

University of Amsterdam Computer Systems – cache characteristics Arnoud Visser 1 Computer Systems Cache characteristics.
Virtual Memory. Hierarchy Cache Memory : Provide invisible speedup to main memory.
MEMORY ORGANIZATION Memory Hierarchy Main Memory Auxiliary Memory
1 Copyright © 2012, Elsevier Inc. All rights reserved. Chapter 2 (and Appendix B) Memory Hierarchy Design Computer Architecture A Quantitative Approach,
Input-output and Communication Prof. Sin-Min Lee Department of Computer Science.
Multilevel Memory Caches Prof. Sirer CS 316 Cornell University.
6/12/2015Page 1 Exploiting Memory Hierarchy Chapter 7 B.Ramamurthy.
How caches take advantage of Temporal locality
Recap. The Memory Hierarchy Increasing distance from the processor in access time L1$ L2$ Main Memory Secondary Memory Processor (Relative) size of the.
Caching I Andreas Klappenecker CPSC321 Computer Architecture.
CSCE 212 Quiz 11 – 4/13/11 Given a direct-mapped cache with 8 one-word blocks and the following 32-bit memory address references: 1 2, ,
Cache memory October 16, 2007 By: Tatsiana Gomova.
CMP 301A Computer Architecture 1 Lecture 4. Outline zVirtual memory y Terminology y Page Table y Translation Lookaside Buffer (TLB)
Cache Control and Cache Coherence Protocols How to Manage State of Cache How to Keep Processors Reading the Correct Information.
CSCI 232© 2005 JW Ryder1 Cache Memory Organization Direct Mapping Fully Associative Set Associative (very popular) Sector Mapping.
1 CMPE 421 Advanced Computer Architecture Accessing a Cache PART1.
Computer Organization and Architecture Tutorial 1 Kenneth Lee.
1  2004 Morgan Kaufmann Publishers Chapter Seven Memory Hierarchy-3 by Patterson.
CS2100 Computer Organisation Virtual Memory – Own reading only (AY2015/6) Semester 1.
Protection of Processes Security and privacy of data is challenging currently. Protecting information – Not limited to hardware. – Depends on innovation.
Logical & Physical Address Nihal Güngör. Logical Address In simplest terms, an address generated by the CPU is known as a logical address. Logical addresses.
Additional Slides By Professor Mary Jane Irwin Pennsylvania State University Group 1.
Virtual Memory 1 Computer Organization II © McQuain Virtual Memory Use main memory as a “cache” for secondary (disk) storage – Managed jointly.
High Performance Computing1 High Performance Computing (CS 680) Lecture 2a: Overview of High Performance Processors * Jeremy R. Johnson *This lecture was.
Memory Hierarchy and Cache Design (3). Reducing Cache Miss Penalty 1. Giving priority to read misses over writes 2. Sub-block placement for reduced miss.
The University of Adelaide, School of Computer Science
COSC2410: LAB 19 INTRODUCTION TO MEMORY/CACHE DIRECT MAPPING 1.
Memory Management & Virtual Memory. Hierarchy Cache Memory : Provide invisible speedup to main memory.
CSCI206 - Computer Organization & Programming
VIRTUAL MEMORY.
Tutorial Nine Cache CompSci Semester One 2016.
Cache Memory and Performance
Memory COMPUTER ARCHITECTURE
CS161 – Design and Architecture of Computer
The University of Adelaide, School of Computer Science
Memory Hierarchy Virtual Memory, Address Translation
Consider a Direct Mapped Cache with 4 word blocks
CACHE MEMORY.
Computer Architecture
CHAPTER 8: CPU and Memory Design, Enhancement, and Implementation
Assignment 4 – (a) Consider a symmetric MP with two processors and a cache invalidate write-back cache. Each block corresponds to two words in memory.
Exploiting Memory Hierarchy Chapter 7
CSCI206 - Computer Organization & Programming
Lecture 21: Memory Hierarchy
Lecture 21: Memory Hierarchy
CSCI206 - Computer Organization & Programming
FIGURE 12-1 Memory Hierarchy
Chapter 5 Memory CSE 820.
Systems Architecture II
Interconnect with Cache Coherency Manager
Lecture 22: Cache Hierarchies, Memory
Help! How does cache work?
Computer System Design (Processor Design)
Direct Mapping.
Module IV Memory Organization.
Chap. 12 Memory Organization
CMSC 611: Advanced Computer Architecture
Cache Memory.
ECE232: Hardware Organization and Design
Miss Rate versus Block Size
Computer System Design Lecture 9
Word Assembly from Narrow Chips
Lecture 13: Cache Basics Topics: terminology, cache organization (Sections )
Cache Memory.
Memory Management & Virtual Memory
Presentation transcript:

CSCI2510 Tutorial 5 Introduction to Cache Zong Wen

Cache Cache was the name chosen to represent the level of the memory hierarchy between the processor and main memory in the first commercial computer to have this extra level

Direct Mapping Cache

Terms cache block - The basic unit for cache storage. May contain multiple bytes/words of data. cache line - Same as cache block. tag - A unique identifier for a group of data. Because different regions of memory may be mapped into a block, the tag is used to differentiate between them. valid bit - A bit of information that indicates whether the data in a block is valid (1) or not (0)

Address decomposition

Accessing the cache

Reference Computer Organization and Design, The Hardware Software Interface, 3 rd Edition