Digital Logic & Design Dr. Waseem Ikram Lecture No. 35

Recap Serial In/Shift Right/Serial Out Serial In/Shift Left/Serial Out D flip-flop Shift Right Register Universal Serial register

Recap Serial In/Parallel Out Parallel In/Serial Out Parallel In/Parallel Out Universal Shift register

Recap Rotate Right Operation Rotate Left Operation Johnson Counter Ring Counter

11-bit Serial Data format 00/1 11 Stop Bit Data bitsStop bits

Series-to-Parallel Converter

Keyboard Encoder circuit

OLMC of the GAL22V10 device

Software Mode Specification XPIN 22ISTYPE ‘reg’; YPIN 23ISTYPE ‘com’; XPIN 22ISTYPE ‘reg.buffer; ZPIN 20ISTYPE ‘reg.invert’; X := D; X.CLK = Clock; X := D; Y = D;

Assignment Operators for Registered Mode The assignment operators ‘:=’ and ‘:>’ are used in logic descriptions to indicate a Registered output. X := D; Y = D;

ABEL Input file of an 8-bit register with inverted outputs Clock, D0, D1, D2, D3, D4, D5, D6 D7 PIN1, 2, 3, 4, 5, 6, 7, 8, 9; Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 PIN22, 21, 20, 19, 18, 17, 16, 15 ISTYPE ‘reg.invert’;

ABEL Input file of an 8-bit register with inverted outputs The logical declarations are [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7] := [D0, D1, D2, D3, D4, D5, D6, D7]; [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7].CLK = Clock;

ABEL Statements for implementing an 8-bit register with inverted outputs The pin declarations are Clock, D0, D1, D2, D3, D4, D5, D6 D7 PIN1, 2, 3, 4, 5, 6, 7, 8, 9; Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7PIN22, 21, 20, 19, 18, 17, 16, 15 ISTYPE ‘reg.invert’; The logical declarations are [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7] := [D0, D1, D2, D3, D4, D5, D6, D7]; [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7].CLK = Clock; The logical declarations can also be written as Q0 := D0; Q0.CLK = Clock; Q1 := D1; Q1.CLK = Clock; Q2 := D2; Q2.CLK = Clock; Q3 := D3; Q3.CLK = Clock; Q4 := D4; Q4.CLK = Clock; Q5 := D5; Q5.CLK = Clock; Q6 := D6; Q6.CLK = Clock; Q7 := D7; Q7.CLK = Clock;

ABEL Input file of an 8-bit register with inverted outputs The logical declarations can also be written as Q0 := D0; Q0.CLK = Clock; Q1 := D1; Q1.CLK = Clock; Q2 := D2; Q2.CLK = Clock; Q3 := D3; Q3.CLK = Clock; Q4 := D4;

ABEL Input file of an 8-bit register with inverted outputs Q4.CLK = Clock; Q5 := D5; Q5.CLK = Clock; Q6 := D6; Q6.CLK = Clock; Q7 := D7; Q7.CLK = Clock;

GAL22V10 configured as an 8-bit inverted output register OLMC Input/Output ENB 8 OLMC ENB 10 OLMC ENB 12 OLMC ENB 14 OLMC ENB 16 OLMC ENB 16 OLMC ENB 14 OLMC ENB 12 OLMC ENB 10 OLMC Input/Output ENB 8 GAL22V10 Clock D0 D1 D2 D3 D4 D5 D6 D7 Input 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q

8-bit Serial In/Parallel Out Shift Register

Module Right_ bit _ shift _ register Title ‘8-bit shift register in a GAL22V10’ “Device Declaration RegisterDevice‘P22V10 “Pin Declaration Clock, ClearPin1, 2; Data, EnablePin 3, 4; Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 Pin 16, 17, 18, 19, 20, 21, 22, 23 I STYPE ‘reg.buffer’ Equations Q0 := Data & Enable; [Q1, Q2, Q3, Q4, Q5, Q6, Q7]

Equations Q0 := Data & Enable; [Q1, Q2, Q3, Q4, Q5, Q6, Q7] := [Q0, Q1, Q2, Q3, Q4, Q5, Q6]; [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7].CLK = clock; [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7].AR = !clear;

Test_Vectors ([Clock, Clear, Data, Enable] -> [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]) [.x., 0,.x.,.x. ] -> [0, 0, 0, 0, 0, 0, 0, 0 ]; [.c., 1, 1, 0 ] -> [0, 0, 0, 0, 0, 0, 0, 0 ]; [.c., 1, 0, 1 ] -> [0, 0, 0, 0, 0, 0, 0, 0 ]; [.c., 1, 1, 1 ] -> [1, 0, 0, 0, 0, 0, 0, 0 ]; [.c., 1, 0, 1 ] -> [0, 1, 0, 0, 0, 0, 0, 0 ]; [.c., 1, 1, 1 ] -> [1, 0, 1, 0, 0, 0, 0, 0 ]; [.c., 1, 0, 1 ] -> [0, 1, 0, 1, 0, 0, 0, 0 ]; [.c., 1, 1, 1 ] -> [1, 0, 1, 0, 1, 0, 0, 0 ]; [.c., 1, 0, 1 ] -> [0, 1, 0, 1, 0, 1, 0, 0 ]; [.c., 1, 1, 1 ] -> [1, 0, 1, 0, 1, 0, 1, 0 ]; [.c., 1, 0, 1 ] -> [0, 1, 0, 1, 0, 1, 0, 1 ]; [.c., 1, 1, 1 ] -> [1, 0, 1, 0, 1, 0, 1, 0 ]; [.c., 0, 1, 1 ] -> [0, 0, 0, 0, 0, 0, 0, 0 ]; END

4-bit Parallel In/Serial Out Shift Register

Shift Register Applications Series to Parallel Converter Serial data format (fig 1) Series to parallel converter circuit (fig 2) Keyboard Encoder (fig 3)

Programmable Sequential Logic Registered Mode OLMC circuit (fig 4) Software Mode Specification (fig 5) Example1 ABEL input file of 8-bit Register with inverted output (fig 6a) GAL22V10 diagram of register (fig 6b) Example2 8-bit Serial In/ Parallel Out Shift Register implemented using logic gates (fig 7) ABEL input file of shift Register (fig 8)

Programmable Sequential Logic Example3 4-bit Parallel In/ Serial Out Shift Register implemented using logic gates (fig 9) ABEL input file of shift Register (fig 10) Example4 3-bit Up/Down counter using D flip-flops (tab 1,2 fig 11) ABEL input file of Counter (fig 12)

Module Four_bit_shift_register Title ‘4-bit shift register in a GAL22V10’ “Device Declaration RegisterDevice‘P22V10’ “Pin Declaration Clock, ClearPin 1, 2; SHLDPin 3; D0, D1, D2, D3Pin 4, 5, 6, 7 ISTYPE ‘reg.buffer’; Q0, Q1, Q2, Q3Pin 14, 15, 16, 17 ISTYPE ‘reg.buffer’; Equations Q0 := D0; Q1 := Q0 & SHLD # D1 & !SHLD; Q2 := Q1 & SHLD # D2 & !SHLD;

Q3 := Q2 & SHLD # D3 & !SHLD; [Q0, Q1, Q2, Q3].CLK = clock; [Q0, Q1, Q2, Q3].AR = !clear; Test_Vectors ([Clock, Clear, SHLD, D0, D1, D2, D3] -> [Q3]) [.x., 0,.x.,.x.,.x.,.x.,.x. ] -> [ 0 ]; [.c., 1, 0, 0, 1, 0, 1 ] -> [ 1 ]; [.c., 1, 0, 1, 0, 1, 0 ] -> [ 0 ]; [.c., 1, 1, 1, 0, 1, 0 ] -> [ 1 ]; [.c., 1, 1, 1, 0, 1, 0 ] -> [ 0 ]; [.c., 1, 1, 1, 0, 1, 0 ] -> [ 1 ]; [.c., 0, 0, 1, 0, 1, 0 ] -> [ 0 ]; END