ALPHA 21164PC

Alpha 21164PC High-performance alternative to a Windows NT Personal Computer

21164 Alpha Chip One of the highest performing microprocessor speeds topping one billion instructions per second quad-issue and superscalar in architecture

Advantages speed factor manufacturing systems with greater simplicity manufacturing systems with lower cost run at a low voltage rate of 3.3 volts runs on various platforms such as both UNIX and windows

Advanced Structure virtual instruction caching seven-bit address space numbers on chip dual read ported data cache out of order instruction completion on chip three way set instruction completion third level cache parameters

Some Design Goals reduced cost higher performance reduced power time to market

Reduction Factors Required two elements –die size reduction –remove processing steps

Layout conversion strategy Thirty percent linear shrink was not feasible to compensate 25% linear shrinkage was used

Speed How fast do you want to go today? 400Mhz, 466mhz, or 533Mhz

Speed Design based upon a single-wire two phase clocking plan 14 gates per cycle including the latches single global clock grid (global clock skew<90ps, local clock skew<25ps)

Initial Conversion Problems most programs had to be converted before they could be run on an alpha system This was because the alpha processor was designed as a 64bit system when it came out, and all of the other systems on the market were still 32bit This caused a problem with running the ‘standard’ 32bit programs on a 64bit processor

Conversion Solution had to come up with software that could covert a 32bit program to run on a 64bit machine. used a program called FX!32

The Chip 0.5 micrometer CMOS process Operation frequency of 300MHz 5 functional units 3 cache memory 9.3 Million transistors VLSI - Very Large Scale Integration

Registers Standard Registers Program Counter Stack Pointer Process Status Unique to the alpha floating point point register

The Cache Memory on the Chip

Cache Memory Instruction Cache –8KB of first level cache Data Cache –8KB of first level cache Set-Associative Cache –96KB of second level cache –holds both instructions and data

The Five Functional Units on the Chip:

The Instruction Unit Contains an 8KB, direct-mapped instruction cache, an instruction prefetcher and associated refill buffer, branch prediction logic, and an instruction translation buffer (ITB). The instructional unit retrieves commands from the cache, distributes them to the appropriate functional units, after resolving any conflicts. It controls all program flow, interrupt handling, and controls all data bypasses and register file writes. The cache consists of 32 byte blocks that contain virtual address information.

Integer Unit Used to execute all of the operation instructions that are to be performed on integers. They receive their instructions from the instruction unit and direct their information to the appropriate pipelines.

The Floating-Point Unit Used to execute all of the operation instructions that are to be performed on floating-point numbers. They also receive all of their instructions from the instruction unit and send the correct information to the appropriate pipelines.

The Memory Unit Contains a fully associative 64-entry, data translation buffer, a direct mapped primary cache, the miss address file, and a write buffer. Allows the system to store and access information

The Bus Interface Unit This unit contains and manages the second level set- associative cache. Allows the system interface to access the I/O and the memory.

Alpha 21164PC 64-bit Processor RISC

Alpha 21164PC Superpipelined Superscalar

Alpha 21164PC Other Technologies

ALPHA 21164PC

Why Businesses Use Alpha Systems Exceptional internet services high-performance technical applications accomplish more work in less time greatly reduce their costs in man hours

Role in the Market Place Compaq Windows NT 5.0 Outperforms TWO Pentium II’s Costs Less