Tomasz Hemperek, STATUS OF DHPT 1.0 PXD/SVD Workshop 5 th February 2013

DHP – Data Handling Processor 2 Area 12.5 mm 2 >1Mbit SRAM memory >200k gates 155 I/O pads (CMOS and LVDS) 1.6 Gbit/s output link JTAG configuration 11 DACS 10 bit ADC Temperature sensor DHPT 1.0 TSMC 65nm Current Prototype: DHP 0.2 – IBM 90nm

DHPT 1.0 Planner 3

Run Modes 4 Trigger On Trigger Off Veto Run Stop Data Dump Trigger line is not anymore level sensitive! Commands are Manchester coded (4bit) send on trigger line. Controls readout Starts Gated Mode sequence Standard operation mode Raw data transfer

New Sequencer rows 4x32 columns switcher clock switcher data switcher clear switcher gate veto run run mode memory gated mode memory 2 memories for run mode and gated mode Gated mode started be trigger command (at given row) stopped after programmable time All switcher signals can be adjusted individually bit by bit (3.125ns) Memory protected by Hamming code, refreshed every frame

Memory organization – raw data & pedestals 6 DHP x1024x32 (2 frames) DHPT 1.0 4x1536x128 (3 frames) Overall memory size: 3 frames (1x data + 2x pedestal) Double buffer for pedestals: one is active one gets updated in the background (JTAG) Toggle memories once update is finished Memory protected by Hamming code

Other 7 Improve DCD clock transmission (320 MHz on single ended line) It is possible to send differential clock to DCD by keeping backward compatibility Use of synchro output on DCD (currently unused) Alternative: single ended low swing clock input od DCD Increase of FIFO depth Anything else?  Have a dedicated meeting for discussion on DHPT1.0 changes/improvements

Plan 8 FebruaryMarchApril Digital Design Verification Implementation Analog Designs Sign-off

Questions? 9