Interrupts

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 2 Learning Objectives  Introduction to interrupts.  Types of interrupts and sources.  Interrupt timeline.  Handling and processing interrupts using C and assembly code.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 3Introduction  Interrupts are used to interrupt normal program flow, so that the CPU can respond to events like I/O demands  An alternative to Interrupt is polling, where the program continuously tests whether data is available to be received or transmitted

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 4Introduction  Servicing an interrupt involves saving the context of the current process, completing the interrupt task (interrupt service routine), restoring the process context, and resuming the original process.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 5Introduction

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 6 Interrupt Sources  Types of interrupts on the ‘C6000 CPUs  RESETHighest priority  NMI  INT4  INT5  INT6  INT7  INT8  INT9  INT10  INT11  INT12  INT13  INT14  INT15Lowest priority

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 7 Interrupt Sources  The RESET signal resets the CPU and has the highest priority.  NMI, the non-maskable interrupt, is the second–highest priority interrupt and is generally used to alert the CPU of a serious hardware problem such as an imminent power or memory failure [A non-maskable interrupt means that the interrupt cannot be ignored or disabled by the system].  INT4-INT15 are maskable interrupts which means that the processor can mask or temporarily ignore the interrupt if it needs to, so it can finish something else that it is doing. These interrupts can be associated with external devices, on–chip peripherals, software control, or not be available.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 8 Interrupt Control Registers  There are eight registers in the ‘C6713 that control servicing interrupts.  Interrupt Control Registers  CSR (control status register): contains the global interrupt enable (GIE) bit and other control/status bits  IER (interrupt enable register): enables/disables individual interrupts  IFR (interrupt flag register): displays status of interrupts – if interrupt is pending  ISR (interrupt set register): sets pending interrupts  ICR (interrupt clear register): clears pending interrupts  ISTP (interrupt service table pointer): locates an ISR  IRP (interrupt return pointer)  NRP (non-maskable interrupt return pointer)

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 9 Generating a Maskable Interrupt  An appropriate transition on an interrupt pin sets the pending status of the interrupt within the interrupt flag register (IFR). If the interrupt is properly enabled (conditions on next slide), the CPU begins processing the interrupt and redirecting program flow to the interrupt service routine.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 10 Generating a Maskable Interrupt  The following conditions must be met to process a maskable interrupt:  The global interrupt enable bit (GIE) bit in the control status register (CSR) is set to 1  The NMIE bit in the interrupt enable register (IER) is set to 1  Corresponding interrupt enable (IE) bit in the IER is set to 1  The corresponding interrupt occurs, which sets the corresponding bit in the IFR to 1 and there are no higher priority interrupt flag (IF) bits set in the IFR.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 11 Generating a Maskable Interrupt  The conditions for an interrupt to be handled: Interrupt Source *Map Interrupt 4-15 Transition IFR =1 for INT x Process Interupt *GIE = 1 (not masking) *NMIE = 1 NMI enabled *IE for INT = 1 enabled No higher IFR = 1 ProcessInterrupt

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 12 Mapping Interrupt Sources to CPU Interrupts CPU Int RESET RESET NMI NMIreservedreserved INT4 INT4 INT5 INT5INT6INT7INT8INT9INT10INT11INT12INT13INT14INT15Sources (HPI) DSPINT TINT0TINT1SD_INTEXT_INT4EXT_INT5EXT_INT6EXT_INT7DMA_INT0DMA_INT1DMA_INT2DMA_INT3XINT0RINT0XINT1RINT1 Description HPI Interrupt Timer 0 Timer 1 SDRAM Refresh External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 McBSP Channel 0 TX McBSP Channel 0 RX McBSP Channel 1 TX McBSP Channel 1 RX PriorityHighLow Note that there are more sources of interrupt than the CPU can handle.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 13 Interrupt Selection CPU Int RESET RESET NMI NMIreservedreserved INT4 INT4 INT5 INT5INT6INT7INT8INT9INT10INT11INT12INT13INT14INT15Sources (HPI) DSPINT TINT0TINT1SD_INTEXT_INT4EXT_INT5EXT_INT6EXT_INT7DMA_INT0DMA_INT1DMA_INT2DMA_INT3XINT0RINT0XINT1RINT1 Description HPI Interrupt Timer 0 Timer 1 SDRAM Refresh External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 McBSP Channel 0 TX McBSP Channel 0 RX McBSP Channel 1 TX McBSP Channel 1 RX PriorityHighLow Each source interrupt can be made to trigger a specific CPU interrupt.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 14 Interrupt Selection  The interrupt source mapping can be achieved by initializing the appropriate bit-fields of the interrupt multiplexer.  Each CPU interrupt has a selection number “INTSEL#” that specifies the source. Interrupt Multiplexer High Interrupt Multiplexer High ( INT10 - INT15 ) (address 0x19c0000) Interrupt Multiplexer Low Interrupt Multiplexer Low ( INT4 - INT9 ) (address 0x19c0004)2629INTSEL152124INTSEL141619INTSEL131013INTSEL1258INTSEL1103INTSEL INTSEL92124INTSEL81619INTSEL71013INTSEL658INTSEL503INTSEL4

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 15 Interrupt Selection  Example: Mapping EXT_INT5 to CPU INT12. Interrupt Multiplexer High Interrupt Multiplexer High ( INT10 - INT15 ) (address 0x19c0000) Interrupt Multiplexer Low Interrupt Multiplexer Low ( INT4 - INT9 ) (address 0x19c0004)2629INTSEL152124INTSEL141619INTSEL131013INTSEL1258INTSEL1103INTSEL INTSEL92124INTSEL81619INTSEL71013INTSEL658INTSEL503INTSEL x19c0000 0x19c0004 address Write 5 dec = 0101b to INTSEL12

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 16 Interrupt Selection  Writing code to initialize INT12 with 0101b, there are 3 methods: (1) Using assembly: (2) Using the Chip Support Library (CSL): MVKL0x19c0000, A1 MVKH0x19c0000, A1 LDW*A1, A0 CLRA0, 10, 13, A0 SETA0, 10, 10, A0 SETA0, 12, 12, A0 STWA0, *A1 #include #include IRQ_map (IRQ_EVT_EXTINT5, 12);

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 17 (3) Using the GUI interface:  Open the CDB file.  Select Hardware Interrupt Service Routine Manager.  Select the CPU interrupt 12 (HWI_INT12) and right click and select properties.  Select External_Pin_5 as the interrupt source. Interrupt Selection

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 18 Interrupt Processing Configure 1. Select interrupt sources and map them. 2. Create interrupt vector table. Enable 3. Enable individual interrupts. 4. Enable global interrupt. 5. Check for valid signal. 6. Once a valid signal is detected set flag bit. 7. Check if interrupt is enabled, if yes branch to ISR. 8. Write context store routine. 9. Write the ISR. 10.Write context restore routine. 11.Return to main program. User Responsibility (Initialization) Performed by the CPU User Responsibility (Algorithm)

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 19 Creating an Interrupt Vector  When an interrupt occurs, the CPU automatically recognizes the source of the interrupt and jumps to the interrupt vector location.  In this location a program is found which instructs the processor on the action(s) to be taken.  Each vector location can accommodate eight instructions which correspond to a fetch packet.  Such a location is known as the Interrupt Service Fetch Packet (ISFP) address.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 20 Interrupt Service Table  The IST is a table of fetch packets that contain code for servicing the interrupts.  The IST consists of 16 consecutive fetch packets.  Each interrupt service fetch packet (ISFP) contains eight instructions used to service the interrupt. One of the instructions is a branch to the interrupt return pointer instruction (B IRP).  The IST is located at addresses 0h - 200h 16 fetch packets in the table, each fetch packet is of 8 instructions of 32 bits/instruction or = 32 bytes. 16*32=512bytes=200h

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 21 Creating an Interrupt Vector  The following table shows the interrupt sources and associated ISFP addresses:

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 22 Creating an Interrupt Vector  Example 1: ISR fits into a single Fetch Packet (FP).

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 23 Creating an Interrupt Vector  Example 2: ISR fits into multiple successive FP’s (assuming the next interrupts are not used).

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 24 Creating an Interrupt Vector  Example 3: ISR is situated outside the interrupt vector table. RESET NMI Res INT4 INT5 INT6 B IRP NOP 5 0x0000 0x0020 0x0080 MVK MVKH B ISR LDH MVC STR ZERO Branch to ISR after executing the FP ISR Return from interrupt after executing the ISR

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 25 Relocating the Vector Table Relocating the Vector Table  In general the vector table or the section “vectors” is linked to address zero.  However in many applications there is a need to change the location of the vector table.  The location of the interrupt vector table is set in the.cmd file under the segment marked.vec  In the C6713dsk.cmd file the vector table is placed at address 0  The IST, with the addresses of the ISR of the different interrupt source, can also be found in the vectors.asm file

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 26 Relocating the Vector Table  This is due to many factors such as:  Moving interrupt vectors to fast memory.  Having multiple vector tables for use by different tasks.  Boot ROM already contained in memory starting at address 0x0000.  Memory starting at location zero is external and hence there will be a need to move the vector table to internal memory to avoid bus conflict in shared memory system.  In order to relocate the vector table, the Interrupt Service Table Pointer (ISTP) register should be set up.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 27 Relocating the Vector Table reservedISTB ISTP

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 28 Relocating the Vector Table Relocating the Vector Table  Example: Relocate the ISTP to address 0x800. (1) The interrupt vector code located between 0x000 and 0x200 must be copied to the location 0x800 and 0x x200 (0xA00). (2) Initialize the ISTP. MVKL0x800, A0 MVKH0x800, A0 MVCA0, ISTP

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 29 nmie1rsvrsvIE4IE5IE6IE7IE8IE9IE10IE11IE12IE13IE14IE Reserved R, W, +0 R,+1 Enable Individual Interrupts (in IE Register)  Example: Write some code to enable INT7.  To enable each int, write “ 1 ” to IE bit  IER bits are NOT affected by the value in global interrupt enable (GIE)

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 30 _asm_set_INT7 MVC.S2 IER, B0 SET.L2 B0,7, 7, B0 MVC.S2 B0, IER Enable Individual Interrupts  Method 1: Using “C” code. #include #include void enable_INT7 (void) { IER = IER | 0x040; }  Method 2: Using assembly. #include #include IRQ_enable (IRQ_EVT_EXTINT7)  Method 3: Using the CSL.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 31 Enable Global Interrupt (In CS Reg.)  IER allows the enabling or disabling of interrupts individually.  GIE bit allows the enabling or disabling of interrupts globally (all at once). Note: By disabling GIE, interrupts can be prevented from occurring during initialization. NMI INT15 IER CSR GIE ‘C6000CPU RESET GIE

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 32 _asm_set_GIE MVC.S2 CSR, B0 SET.L2 B0,0, 0, B0 MVC.S2 B0, CSR Enable Global Interrupt  Method 1: Using “C” code. #include #include void enable_GIE (void) { CSR = CSRIER | 0x1; }  Method 2: Using assembly. #include #include IRQ_globalEnable ()  Method 3: Using the CSL.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 33 Check for a Valid Signal Conditions for recognition of an external interrupt:  The interrupt must be held low for at least 2 cycles then high for at least two cycles. Recognition of the interrupt:  The interrupts are latched on the rising edge of CLKOUT1.  The interrupt is finally recognized by the CPU one cycle after being latched. INTx CPU Clock (CLKOUT1) Interrupt latched Interrupt recognized by CPU Occurrence of Interrupt 2 cycles minimum

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 34 Interrupt Flag Register (IFR)  When an interrupt is recognized, the corresponding bit in the IFR is set:  e.g. if INT7 is recognized, then IFR[7] bit is set. IER CSR GIE ‘C6000CPU RESET GIE IFR 0 0 INT7 0 INT15 INT7 1

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 35 What Happens When an Interrupt Occurs?  The corresponding bit in the IFR is set to 1  If GIE=1 (interrupts are globally enabled), and no higher priority interrupts are pending, the interrupt is serviced:  GIE is cleared to preclude other interrupts  The flag bit in the IFR is cleared  The return address is put in the IRP  When CPU interrupt INT_n occurs, program execution jumps to byte offset 32n in the interrupt service table (IST) (each entry in the table is eight instructions long)

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 36 What Happens When an Interrupt Occurs?  An ISFR (Interrupt Service Fetch Packet) may contain the entire service routine, or it may branch to a larger service routine  The service routine must save the CPU state on entry (save registers on stack), and restore it on exit  A return from interrupt is accomplished by the assembly instruction B IRP where IRP holds the return address to the main program

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 37 CPU Interrupt Hardware Sequence What does the CPU do when an interrupt is recognized? CPU Action Description 0  IFR (bit) Clears corresponding interrupt flag bit GIE  PGIE Save previous value of GIE 0  GIE Disables global interrupts Save next EP address Save return address in IRP/NRP Vector (ISTP)  PC Loads PC with interrupt vector addr 1  IACK pin IACK is asserted INUM(0-3) INUM pins display corresponding int IACK and INUM pins are only available on the C620x and C670x.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 38 xxxx xxxx CPU Interrupt Hardware Sequence e.g. if INT7 is recognized and IER[7] is set: IFR CSR 110 0x PC 0x INT7 -> 0x ADD A0, A1, A2 0x MPY A2, A6, A7 0x MPY A2, A6, A7 0x IRP

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 39 Writing the ISR in C There are two methods of declaring an ISR: (1)Traditional method: interrupt void ISR_name (void); main (void) {...} interrupt void ISR_name (void) {...} Notes:  You need to use the interrupt keyword in order to inform the compiler that it is an ISR, and therefore to handle the necessary register preservation and use the IRP for returning from the interrupt.  No arguments can be passed to the ISR.  No argument can be returned.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 40 Writing the ISR in C (2) Using the dispatcher in DSP/BIOS: Notes:  You do not need to use the interrupt keyword.  Interrupt nesting of interrupt functions written in “C” is allowed.  You can pass one argument.  You can specify which interrupts can be nested by specifying a mask. Insert figure

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 41 Writing the ISR in Assembly  For maskable interrupts the return from interrupt address is always stored in the Interrupt Return Pointer (IRP).  For non-maskable interrupts the address is stored in the Non-maskable Return Pointer (NRP).

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 42 Writing the ISR in Assembly _isr_functionstw...ldh...ldw... b irp nop 5 (1) Save any registers used by the ISR on the stack (2) Use the HWI macros, or (3) Use the hardware interrupt dispatcher Put your ISR code here (1) Restore the registers saved on the stack (2) Use the HWI macros, or (3) Use the HWI dispatcher Return (You can also use HWI macros) It is much simpler to use the HWI dispatcher rather than doing the save and restore of registers by yourself or the HWI_enter and HWI_exit macros.

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 43 Interrupts and the AIC23 Codec  Reading input samples from an input signal and writing output samples to generate an output signal are done by the AIC23 codec (through the processor serial port McBSP)  This device includes an A/D and D/A converters.  When inputting samples, the A/D converter may interrupt the processor when a valid sample is available  When outputting samples, the D/A converter may interrupt the processor when it is ready to receive the next sample

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 44 Interrupts and the AIC23 Codec

The Codec Block Diagram  Includes  ADC  DAC  Anti-aliasing Filter  Smoothing output filter  Clock generator for the sampling rate and bit IO  RLINEIN, LLINEIN – analogue line in inputs  MICIN – Microphone input  ROUT, LOUT – analogue output lines  RHPOUT, LHPOUT – headphone output lines  DOUT – the digital converted data, converted by the ADC, output serially  DIN – The digital data in to be converted by the DAC, input serially

Codec Initialization

Codec Interrupt

Interrupt Vector.ref _c_int00 ;entry address VEC_ENTRY.macro addr ;macro for ISR STW B0,*--B15 STW B0,*--B15 MVKL addr,B0 MVKL addr,B0 MVKH addr,B0 MVKH addr,B0 B B0 B B0 LDW *B15++,B0 LDW *B15++,B0 NOP 2 NOP 2 NOP NOP.endm.endm_vec_dummy: B B3 B B3 NOP 5 NOP 5.sect ".vecs".sect ".vecs".align 1024 ;aligned IST section.align 1024 ;aligned IST section_vectors: _vector0: VEC_ENTRY _c_int00 ;RESET _vector1: VEC_ENTRY _vec_dummy ;NMI _vector2: VEC_ENTRY _vec_dummy ;RSVD _vector3: VEC_ENTRY _vec_dummy _vector4: VEC_ENTRY _vec_dummy _vector5: VEC_ENTRY _vec_dummy _vector6: VEC_ENTRY _vec_dummy _vector7: VEC_ENTRY _vec_dummy _vector8: VEC_ENTRY _vec_dummy _vector9: VEC_ENTRY _vec_dummy _vector10: VEC_ENTRY _vec_dummy _vector11: VEC_ENTRY _c_int11 ;ISR address _vector12: VEC_ENTRY _vec_dummy _vector13: VEC_ENTRY _vec_dummy _vector14: VEC_ENTRY _vec_dummy _vector15: VEC_ENTRY _vec_dummy The following is the interrupt mapping table, specified in the vectors_intr.asm file. Only interrupt 0 and 11 are specified: The mapping of the codec (MCBSP) interrupt to interrupt 11 is done separately in function comm_intr(), called within the main program

Codec Data Obtained

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 54 Interfacing the Codec and the Processor  The serial port McBSP0 is configured to act as a control channel.  Through this channel the processor sets the codec to function in the desired mode, e.g.  To operate in stereo mode receiving 2x16 bits samples  Setting the desired sampling rate  The serial port McBSP1 is configured to function as the data channel, sending data to the codec, and receiving data from it

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 55 Interrupts and the AIC23 Codec  The first word transmitted by AIC23 is the left channel sample, followed by the right channel sample  The 32-bit word received by McBSP1 from the codec contains the left sample in the upper 16 bits and the right sample in the lower 16 bits.  The 16-bit samples are integers in 2’s complement format  Words sent from the McBSP1 to the codec, must have the same format  It is the codec which generates a sync pulse at the beginning of a sample pair, and the shift clock to send/receive the samples serially

Codec Data Obtained

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 57 Multi-channel Buffered Serial Port (McBSP)  The McBSP serves as a serial data channel to the DSP  Through it, data can be written out or read in by the DSP  The McBSP can generate receive and transmit interrupt to the CPU:  A receive interrupt when it has data for the CPU  A transmit interrupt when it is ready for the next data item to be sent  On the DSK, the serial port uses an external clock from the codec to shift data in and out serially

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 58 McBSP Block Diagram

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 59 McBSP Transmit Block Diagram  The CPU writes a word into the Data Transmit Register (DXR)  The word is loaded into the Transmit Shift Register (XSR), from where it is being shifted out (by the transmit clock)  The McBSP sends an interrupt request to the CPU, after the data has been loaded into the XSR, signaling that it is ready to transmit another word

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 60 McBSP Receive Block Diagram  Data bits are shifted into the Receive Shift Register (RSR) using the receive clock.  When all word bits are in, the RSR register is loaded into the Receive Buffer Register (RBR), and then to the Data Receive Register (DRR)  Then, the McBSP sends an interrupt request to the CPU, indicating that a data word is available for reading

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 61 Codec Interface clock Fs = 8kHz McBSP0McBSP0 CLKR CLKX DRR DXR  Receives all commands and exchanges data serially via McBSP0  Driven by ext. 8kHz clock on DSK board. It drives ‘C6713 serial port 0 (McBSP0) shift clocks.  8kHz sample rate allows maximum sine wave of ______ kHz? 4AIC23:  Has two channels (voice & data), only the voice was used on DSK gain gain AIC23 Voice Channel Data Channel ADC DAC Looking closer at the McBSP...

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 62 McBSP0 gain gain McBSP0 AIC23 Voice Channel Data Channel ADC DAC CLKR CLKX DRR DXR clock Fs = 8kHz BSL Codec Functions AIC23 BSL (DSK Board Support Library) AIC23_open()reserves resource and returns handle AIC23_config() configures McBSP0 and AIC23 AIC23_read()reads from AIC23 ADC thru McBSP0 receive AIC23_write() writes to AIC23 DAC thru McBSP0 transmit AIC23 BSL (DSK Board Support Library) AIC23_open()reserves resource and returns handle AIC23_config() configures McBSP0 and AIC23 AIC23_read()reads from AIC23 ADC thru McBSP0 receive AIC23_write() writes to AIC23 DAC thru McBSP0 transmit

Sending Data from the CPU to AIC23 DAC AIC23McBSP0 speaker xmit D/A 8kHz sample clock CPU sine 150MHz Codec Interface Codec accepts samples at the sampling rate(8kHz) It signals the McBSP when it is ready to receive another sample

XINT0 Interrupt AIC23McBSP0 xmit D/A 8kHz sample clock CPU sine  When McBSP needs another sample, it issues XINT0 HWI  XINT0 should occur at 8kHz (codec sample rate)  How do we make CPU wait? Use loop: while(1);  How do you make an HWI function? Use config tool Codec Interface XINT0 speaker

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 65 Writing samples to the AIC23 Codec  The 32-bit words are sent to the codec by the BSL function DSK6713_AIC23_write()  This function  Polls the McBSP1 XRDY bit, and does not sent the data if the bit is not set.  It sends the sample word by writing it to the Data Transmit Register (DXR) of McBSP1 if XRDY bit is set  The corresponding code is (all functions in CSL Library)

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 66 Reading samples from the AIC23 Codec  32-bit words are read from the codec by the BSL function DSK6713_AIC23_read()  This function  Polls the McBSP1 RRDY bit, and does not read the data if the bit is not set.  It reads the sample word from the Data Receive Register (DRR) of McBSP1 if RRDY bit is set  The corresponding code is (all functions are in CSL Library) :

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 67 Interrupts and the AIC23 Codec  Files for use with the codec:  C6713dsk.cmd – sets up the memory map  C6x.h – defines some of the registers like IER, CSR in C:\ti\c6000\cgtools\include  C6713dsk.h in C:\ti\c6000\dsk6713\include – header file that defines addresses of external memory interface, the serial ports, etc IML, IMH defined here  C6713interrupts.h – contains init functions for interrupt  C6713dskinit.h – header file with the function prototypes  C6713dskinit.c – functions to initialize the DSK, the codec, serial ports, and for input/output.

Setting ISR for XINT0 (McBSP0 Transmit)  In vectors.asm  Interrupt 0 is set for reset – ISR c_int00  Interrupt 11 is set for ISR c_int11  In c6xdskinit.c interrupt 11 is attached to transmit signal XINT0 of the serial port of ‘c6713 (done in comm_intr() using IRQ_map() function)  Each time an interrupt occurs at XINT0 (connected to the codec sampling clock), the ISR c_int11 is executed  This function is defined in the main C program interrupt void c_int11() //interrupt service routine {}

Setting ISR for XINT0 (McBSP0 Transmit)  For example, the ISR for reading an input sample from the ADC and outputting it to the DAC is interrupt void c_int11() //interrupt service routine { int sample_data; int sample_data; sample_data = input_sample(); //input data output_sample(sample_data); //output data return;}

Sending Input Samples Out using Interrupt #include "dsk6713_aic23.h"//codec-DSK support file Uint32 fs=DSK6713_AIC23_FREQ_8KHZ; //set sampling rate void main() { comm_intr(); //init DSK, codec, McBSP comm_intr(); //init DSK, codec, McBSP while(1); //infinite loop while(1); //infinite loop} interrupt void c_int11() //interrupt service routine { short sample_data; short sample_data; sample_data = input_sample(); //input data sample_data = input_sample(); //input data output_sample(sample_data); //output data output_sample(sample_data); //output data}

Sending Input Samples Out using Interrupt  The main program initializes the DSK, the Codec and the McBSP, and then goes into an infinite waiting loop  Each time a sample is available, the c_int11 function is executed, reading an input sample and sending it out  Rather than being engaged in an infinite waiting loop, the main program can perform other tasks.  It will be interrupted each time an input sample is available

Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 10, Slide 72 Polling with the AIC23 Codec  Reading input samples from an input signal and writing output samples to generate an output signal may also be accomplished by polling and the processor serial port  The register used for polling is the Serial Port Control Register (SPCR)  For reading, test bit 1 (second LSB) of the register to see if the port is ready to be read. This is done by doing an AND of the SPCR with 0x2.  For writing, AND SPCR with 0x20000 to test bit 17, the transmit ready bit.

Sending Input Samples Out using Polling #include "DSK6713_AIC23.h" //codec-DSK file support Uint32 fs=DSK6713_AIC23_FREQ_8KHZ; //sampling rate void main() { short sample_data; short sample_data; comm_poll(); //init DSK, codec, McBSP comm_poll(); //init DSK, codec, McBSP while(1)//infinite loop while(1)//infinite loop { sample_data = input_sample(); //input sample sample_data = input_sample(); //input sample output_sample(sample_data); //output sample output_sample(sample_data); //output sample }}

Uint32 input_sample() //for 32-bit input { short CHANNEL_data; if (poll) while(!MCBSP_rrdy(DSK6713_AIC23_DATAHANDLE)); //if ready to receive AIC_data.uint=MCBSP_read(DSK6713_AIC23_DATAHANDLE); //read data return(AIC_data.uint); } void output_sample(int out_data) //for out to Left and Right channels { short CHANNEL_data; AIC_data.uint=out_data; //32-bit data -->data structure if (poll) while(!MCBSP_xrdy(DSK6713_AIC23_DATAHANDLE)); //if ready to transmit MCBSP_write(DSK6713_AIC23_DATAHANDLE,AIC_data.uint); //write/output data }  The polling flag is set by comm_poll(), and then within input sample RRDY bit is polled, and within output sample XRDY bit is polled (see these functions in c6713dskinit.c) Sending Input Samples Out using Polling

 Unlike the implementation with interrupt, when using polling, the main program is always busy waiting for input samples.  The main program cannot be engaged in other tasks  Polling is done in input_sample and output_sample functions  The polling flag is set by comm_poll(), and then within input sample RRDY bit is polled, and within output sample XRDY bit is polled (see these functions in c6713dskinit.c) Sending Input Samples Out using Polling