GOSSIPO-3: Measurements on the Prototype of a Read- Out Pixel Chip for Micro- Pattern Gas Detectors André Kruth 1, Christoph Brezina 1, Sinan Celik 2, Vladimir Gromov 2, Ruud Kluit 2, Francesco Zappon 2, Klaus Desch 1, Harry van der Graaf 2 1 Physics Department, University of Bonn, Nussallee 12, Bonn, Germany 2 National Institute for Subatomic Physics (Nikhef), Science Park 105, 1098 XG Amsterdam, The Netherlands TWEPP, Aachen September 20 th -24 th 2010

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Outline Read-Out of Micro-Pattern Gas Detectors GOSSIPO-3: Features & Architecture Measurement Results and Discussion –Front-End –LDO –TDC Summary & Outlook

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Read-Out of Micro-Pattern Gas Detectors - Particle track image (projection) - 3D track reconstruction - No sensor leakage current compensation - Low parasitic capacitance (less than 10fF) - Micro-discharges in avalanche gap Cluster3 Cathode (Drift) Plane Gas Amplification Structure Cluster2 Cluster1 Read-Out Chip 1mm …1m → Drift Gap 400V 50  m Avalanche Gap Gas-avalanche detector combining a gas layer as signal generator with a CMOS readout pixel array Front-End Circuit C PAR

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 GOSSIPO-3 Features Prototype for a read-out chip in TPCs IBM 130nm CMOS (8 metal layers) 60  m x 60  m pixels (high granularity) Time Measurement mode and Hit Counting mode Local TDC in every pixel Design Goals: –3  W per channel –Arrival time measurement up to 102  s –Arrival time accuracy 1.56ns (one fast VCO bin) –ToT accuracy 200e - accuracy (27ns)

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Pixel Electronics Layout of the pixel LFSR = Counters (data taking) or LFSR = Shift registers (data read-out) Control signals - Clock - TRIGGER (common stop) - TOKEN - RESET Preamp Discr. control Local fast oscillator (640MHz) Local fast oscillator (640MHz) 4 bit Fast counter 8 bit ToT counter 12 bit Slow counter 6 bit Pixel configuration Memory Threshold DAC pad -Threshold - Mask Time / Counting HIT Block diagram of the pixel oscillator Logic: counters & control Preamp & comparator DAC

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 GOSSIPO-3 Architecture 2 LDOs (generate controllable Power Supply Voltage for Ring Oscillators) Pixel (pre-amplifier, comp, Threshold DAC, high resolution TDC, counters & control logic) 3 Front-Ends ( preamp, comp) Ingrid preampBias generating circuit

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Demonstrator Test Set-Up G3 Test Board (dedicated PCB) S3 Multi IO Board (general purpose test board designed by Bonn group) USB Port FPGA External Bias Overwrite -=G3=- Demonstrator Power Regulators CC SRAM

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Front-End Performance Pre-Amplifier with MOS feedback parasitic capacitance C FB about 1fF – high gain Low parasitic input capacitance

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Measurement (averaged)  V=64mV Measurement V PK-PK <20mV Front-End Performance Excellent pre-amplifier noise performance –Charge injection through test pad –Measurement includes output pad driver –ENC ca. 25e - –  NOISE ca. 4mV Simulation Q IN =375e -

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Front-End Performance Pre-amplifer measurement for different channels Metal-Metal Injection Capacitance C TEST Stable high gain Varying time constant of feedback discharge Channel#1 Channel#2 Channel#3 U IN ●C TEST1 /C FB1 U IN ●C TEST2 /C FB2 C TEST and C FB are good reproducible U IN ●C TEST3 /C FB3

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Front-End Performance ToT measurement for different channels Q IN =375e - ToT channel to channel mismatch up to 50% Jitter on TOT rising edge caused by noise on pre- amplifier signal falling edge Cross-talk between channels observed when pad driver switches Channel#1 Channel#2 Channel#3 ToT1 ToT2 ToT3

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Analysis of time variation of the discharge Process variation of small feedback MOS responsible for variation of feedback current Small feedback MOS needed for high gain Front-End Performance Replace picture simulations slope ~ 0.2ns/e - measuremen t

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Front-End Performance Internal delay 9ns assumptotical delay for a charge >6000e - (injection to comperator) Stabilisation needed Replace picture

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 LDO controls supply voltage of fast TDC ring- oscillator (arrival time measurement) Oscillation frequency of f=640MHz in all process corners –Time bin size T=1.56ns –Maximum run time 25ns (16 bins) –V OUT_LDO =0.61V (fast)..1.10V (slow) –Occupancy expectation gives avg. I OUT_LDO =24mA peak I OUT_LDO =44mA –VCO control characteristic allows for  V LDO_OUT =31mV for 25ns LDO Performance

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 LDO Performance Step response to typical load step 20mA –additional external load –inductance of package and bond wires limit response time

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 LDO Performance Settling time to nominal V OUT value for different (external) load steps

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 TDC Performance Counting steps of TDC (input signal directly at digital logic) Replace picture?

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Pixel Performance What do we have here?

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Summary Front-End: –Rise time / internal delay needs to be stabilized –Source of pixel to pixel TOT mismatch identified –High gain / low noise LDOs: –Step response time critical for TDC performance –Close match between simulation and measurement TDC: –???

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Outlook Larger pixel array needed for InGrid test The Gossipo-3 design team joins Timepix II design efforts

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Thanks for your attention!

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Backup Slides

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Pre-Amplifier Schematic

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 Pre-Amplifier Schematic

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 LDO Performance Static R OUT measurement

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 LDO Performance Linearity measurement

A. Kruth, GOSSIPO-3, TWEPP, Aachen, Sept. 20 th -24 th /21 LDO Performance Step response to maximum load step 40mA –additional external load –inductance of package and bond wires limit response time