ECAL electronics schedule JFMAMJJASONDJFMAM Prototype 2 boards Design Layout Fabrication and assembly Testing, including VFE prototype tests Production 9 boards Redesign Layout Fabrication and assembly Testing

ECAL prototype detailed schedule Week VME testsImperial Readout board VME definition Manchester Readout board J0/J2 pin definition RAL/UCL Crate check and backplane wireup RAL JTAG testsRAL Readout board VME tests RAL Readout board VME tests Imperial VFE prototype testsParis Aug Sep Oct Nov

Prototype readout board s/w tests Read/write all registers (and 8MByte memory?) Check trigger and clock inputs from J0 Run FE trigger sequence; observe signals on FPGA legs and outputs on front panel Check configurable parameters change timing sequence Capture data and read out; measure pedestals and noise Measure ADC dynamic range and response to sin wave Ramp DAC and measure response vs. DAC setting Read out in all three modes; unbuffered, semi-buffered and fully buffered. Connect to VFE PCBs and check functionality of system Qu: when do we need front panel cable(s)? How many?

Prototype trigger tests Read/write all registers Check trigger inputs/outputs on J0 and J2 Playback trigger sequences through logic Check configurable parameters change trigger logic Read out trigger data Input external trigger signals and check logic Measure trigger latency and jitter Connect to NIM/LVDS module and check functionality Qu: when do we need NIM/LVDS module and backplane cable?