CRKIT R5 Clock Architecture WINLAB – Rutgers University June 13, 2013 Khanh Le
Zedboard Zynq System Clock Overview PSPL MHz ref clock (IC18, PS_CLK) F7 4 programmable PL clocks 100MHz ref clock (IC17, GCLK) Y9 For portability, use the 100MHz reference clock for PL section (will require one PLL) ref_clk_out (RF ref clock ~30MHz) B19, B20 L18, L19 dac_clk_in (dac ref clock) dac_clk_out (dac source synchronous clock) E19, E20 D18, C19 adc_clk_in (adc source synchronous clock)
Zynq PS System Clocks ARM PLL MHz PS_CLK I/O PLL DDR PLL Mux 6-bit prog. divider 6-bit prog. divider 6-bit prog. divider Mux Clock Ratio Generator cpu_6x4x cpu_3x2x cpu_2x cpu_1x CPU, SCU OCM AXI Interconnect ddr_3x ddr_2x Sync Async 6-bit prog. divider I/O Peripherals USB, Ethernet SDIO, SMC SPI, QSPI, UART CAN, I2C PL PL Clocks Check the clocks on EDK tool !! (REVISIT)
RF Interface dac_data_out[15:0] dac_clk_out dac_frame_out (unused) Not used for word-level, only for Byte- or Nibble-level AD9122 DAC AD9548 Clock Sync AD9523 Clock Gen AD9643 ADC dac_clk_in ref_clk_out(~30MHz) Jitter clean up adc_data_in[13:0] adc_clk_in adc_or_in I Q 1 0 LVDS CMT PLL ODDR (SAME_EDGE Mode) clock feedback DAC Interface RF Reference Clock ADC Interface I2C ? CMT MMCM CTL REG Programmable ref. clock (ug472) 100MHz Rx Baseband D1 D2 Q D1 D2 Q By default, +Rising edge = I +Falling edge = Q +Twos complement Anti-aliasing filter -> Nyquist sampling I Q Q1 Q2 D IDDR (SAME_EDGE_PIPELINED Mode) CMT clock feedback scl sdata I2C -> SPI PCORE INT decimation (LP filtering) Clock domain crossing. Must support fractional synchronization e.g. 125MHz -> 20MHz Tx Baseband Interpolation ? By default, +Rising edge = I +Falling edge = Q +Twos complement + ~1ns skew between data and DCO (DCO delay vs For fractional clock divider CLKOUT1 sys_clk M=3, D=2, O1=5 M=3, D=2, O0=1.5 CLKOUT1 CLKOUT0
ODDR Timing
IDDR Timing
DAC Timing DAC Register Map Default Data bus sampling point is nominally 350ps after each edge of DCI signal, with uncertainty of +/- 300 ps. Data interface timing can be verified using the Sample Error Detection (SED) circuitry (reg 0x07, 0x67-0x73). Reference : AD9122_DAC.pdf
ADC Timing ADC Register Map Interleaved IQ channels : Chan A = I Chan B = Q Reference : AD9643_ADC.pdf ~1ns skew between data and DCO For parallel interleaved mode
Xilinx 7-series Clock Management Tile (CMT) Mixed-mode clock manager Phased-lock loop, subset of MMCM functions 1 CMT = 1 MMCM + 1 PLL Zynq Z-7020 PL clock resources : + 4 CMTs e.g. 4 MMCMs & 4 PLLs + 4 programmable clocks from PS CLKIN only Applications : + clock network deskew + frequency synthesis + jitter reduction
CMT - MMCM Programming port (ug472 + xapp888) Integer counter Independent clock control Fractional counter With Fclkin = 100MHz, M=1, D=1 : Integer divide : O0 = 1 : Fout = 100MHz O1 = 2 : Fout = 50MHz O2 = 3 : Fout = 33.33MHz O3 = 4 : Fout = 25MHz O4 = 5 : Fout = 20MHz O5 = 6 : Fout = 16.66MHz Fout = 80MHz, then O0 = Fclkin/Fout = 100/80 = 10/8 = 1.25 (fractional divide). Fout = 30MHz, O0 = 100/30 = … Alternative, M=3, D=2, O1=5 : CLKOUT1 = 30MHz (rf ref clock) M=3, D=2, O0=1.5 : CLKOUT0 = 100MHz (system clock) With Fclkin = 125MHz (ADC sync clock), M=1, D=1 : Fout = 80MHz, O0 = 125/80 = Fout = 20MHz, O0 = 125/20 = 6.25 Attributes : M = CLKFBOUT_MULT_F D = DIVCLK_DIVIDE O = CLKOUT_DIVIDE (ug472, page 79)
CMT - PLL Integer only counter Programming port Attributes : M = CLKFBOUT_MULT_F D = DIVCLK_DIVIDE O = CLKOUT_DIVIDE
CMT - PLL Integer only counter Programming port Attributes : M = CLKFBOUT_MULT_F D = DIVCLK_DIVIDE O = CLKOUT_DIVIDE
MMCM and PLL Use Models (ug472, page 87) Requires two BUFGs Requires only one BUFG + jitter filtering + frequency synthesis + no phase requirement between Fin and Fout Off-chip compensation Input buffers must be in same bank. Use COREGEN to get additional settings information. Restrictions : F FB F in
Clock Distribution e.g. Zedboard Zynq how many APP can be supported ?
Decimation – Fractional Synchronizer
Interpolation ??
Clock Domain Abstraction Layers MOVE TO SEPARATE DESIGN DOCUMENT !