A seminar Presentation on NETWORK- ON- CHIP ARCHITECTURE EXPLORATION FRAMEWORK Under the supervision of Presented by Mr.G.Naresh,M.Tech., V.Sairamya Asst. Professor, Dept. of ECE 15121d5709 SREE VIDYANIKETHAN ENGINEERING COLLEGE (Autonomous) Sree Sainath nagar, A.Rangampet, Tirupathi

1. Introduction 2. NOC Working 3. NOC Architecture 4. NOC Generation flow 5. Simple scalar 6. NOC Fault- Injection Model 7. Simulation Results 8. Conclusion 9. References

 NOC architecture covers the generation of communication infrastructure,automated automated integration of IP-components.  The automated integration of IP-components is based on IP-XACT interface descriptions of these components.  The integration of components into the Network-on-Chip architecture exemplarily for the SimpleScalar Instruction-Set-Simulator (ISS).  The Network-on-Chip architecture used in this paper, is based on a parametrizable switch implemented as Transaction-Level- Model (TLM) in SystemC. The Transaction-Level-Model of the switch provides the possibility of integrating different routing algorithms like deterministic or adaptive routing algorithms

 switch we implemented enables the usage of different routing algorithms. Thereby it is possible to compare different routing algorithms with each other.  Furthermore, our approach does not only cover the automated generation of the communication structure it also enables the automated integration of IP-components into the NoC-architectures.  The integration of the SimpleScalar ISS into NoC-architectures that uses shared memory and Memory Mapped IO (MMIO) for the communication between the ISS and the SystemC simulation model.  Anymore the approaches presented in only take into account the integration of the SimpleScalar into MPSoCs. The usage of more complex communication structures and different routing algorithms.

 Integrate different routing algorithms into the switch, the architecture model enables the parameterization of the transmission technique like store-and-forward data.  The switches are connected to each other with sc fifo channels. These channels model the connection between the switches also as the input- and output-buffers of the connected switches.  The size of the input- and output-buffers can be parametrized in the XML- description file mentioned before write.  Beside the incoming and outgoing ports for the connection to neighboring switches, each switch has a dedicated incoming and outgoing port to a Network-Interface (NI).

IP-Components: are modeled using parts with the stereotype_ ip-component Network-Interfaces: parts annotated with _ network interface Switches: are modeled with parts that are annotated with _switch Ports: are modeled with ports Channels: are modeled by using connectors between two ports 

 The SimpleScalar ISS offers an infrastructure for modeling of different kinds of processors to make their development easier by simulation entire applications on the processor models.  SimpleScalar-Extensions it was necessary to make modifications on some modules of the SimpleScalar software architecture.  SimpleScalar-Connection The SimpleScalar stores data that should be sent in this shared memory and the Network-Interface stores there received data. Network-Interface and SimpleScalar use interrupts to signal each other whether data is available in the shared memory

Simple scalar connection

 The possibility of injecting faults into the NoCs enables the evaluation of the fault tolerance of an NoC-architecture.  Therefore we implemented an error module in SystemC for injecting faults into the simulation model of NoCs. We consider faults as completely broken links and switches or as flipped bits in the transmitted data.  Thereby switches and links are set to broken or the transmitted data is falsified.

 The simulation module can be parametrized concerning the interval of the traffic generation, the amount of data transferred and the communicating components  For simulation, we generated an 8×8 mesh and an 8×8 torus topology and connected one simulation module per switch.  The entire network consists of 64 simulation modules and 64 switches. During simulation we used random traffic, matrix transpose traffic and hot- spot traffic.

 A framework for the automated generation of NoCs, that enables the comparison of different NoC-architectures with different kinds of topologies and different kinds of routing algorithms concerning performance, fault-tolerance, and communication latencies of the entire system.  The proposed generation framework uses a network architecture based on parametrizable switch. That switch is implemented in SystemC as a Transaction-Level-Model and enables the generation of different kinds of topologies.  The generation framework, enables the integration of IPcomponents with different interfaces into the NoC-architecture by using IP-XACT interface descriptions of the IP-components for the generation of Network-Interfaces

 1. L. Benini and G. D. Micheli, “Network on Chips: A New SoC Paradigm,” IEEE Computer, vol. 35, no. 1,  2. A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. O¨ berg, M. Millberg, and D. Lindqvist, “Network on a Chip: An architecture for billion transistor era,” in NORCHIP ’00: Proceedings of the 17th IEEE NORCHIP Conference, 2000  3. V. Narayanan and Y. Xie, “Reliability Concerns in Embedded System Designs,” IEEE Computer, vol. 39, no. 1,  4. S. Borkar, “Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation,” IEEE Micro, vol. 25, no. 6, 2005.