©F.M. Rietti Communication Lines Fundamentals

©F.M. Rietti LM-18 Computer Science SSI Embedded Systems I 2 Communication Lines Generally used to connect external devices –Microcontrollers world has introduced new standards for peripherals interfaces that can be externally wired or internally wired via PCB tracks: –SPI –I2C

©F.M. Rietti LM-18 Computer Science SSI Embedded Systems I 3 Communication Lines (cont) SPI SPI mean S(erial) P(eripheral) I(nterface) The interface was developed by Motorola and has become a “de facto” standard, most used also on microntroller world.Motorola Spi can be considered as a wired bus that can operate with a single master device and with one or more slave devices.

©F.M. Rietti LM-18 Computer Science SSI Embedded Systems I 4 Communication Lines (cont) SPI (cont) –SPI OSI Layer 0 SPI use four wire for exchanging data from peripherals

©F.M. Rietti LM-18 Computer Science SSI Embedded Systems I 5 Communicatons Lines (cont) SPI (cont) Wires meaning –MOSI (Master Out Slave In) [SDO] –MISO (Master In Slave Out) [SDI] –SCK (Slave Clock) [SCK] –SS_n (Slave Select).

©F.M. Rietti LM-18 Computer Science SSI Embedded Systems I 6 Communication Lines (cont) –SPI (cont) To begin communication, the bus master configures the clock, using a frequency supported by the slave device, typically up to a few MHz. The master then selects the slave device with a logic level 0 on the select line. If a waiting period is required, such as for analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles. During each SPI clock cycle, a full duplex data transmission occurs. The master sends a bit on the MOSI line and the slave reads it, while the slave sends a bit on the MISO line and the master reads it. This sequence is maintained even when only one-directional data transfer is intended.

©F.M. Rietti LM-18 Computer Science SSI Embedded Systems I 7 Communication Lines (cont) SPI (cont) –Multi Slave In general, each slave will need a separate SS line. To talk to a particular slave, you’ll make that slave’s SS line low and keep the rest of them high (you don’t want two slaves activated at the same time, or they may both try to talk on the same MISO line resulting in garbled data). Lots of slaves will require lots of SS lines; if you’re running low on outputs, there are binary decoder chips that can multiply your SS outputs.binary decoder chips

©F.M. Rietti LM-18 Computer Science SSI Embedded Systems I 8 Communication Lines (cont) SPI (cont) –Daisy Chain Multi Slave Configured with the MISO (output) of one going to the MOSI (input) of the next. In this case, a single SS line goes to all the slaves. Once all the data is sent, the SS line is raised, which causes all the chips to be activated simultaneously. Note that, for this layout, data overflows from one slave to the next, so to send data to any one slave, you’ll need to transmit enough data to reach all of them. Also, keep in mind that the first piece of data you transmit will end up in the last slave. Each slave must copy input data to output to propagate them.

©F.M. Rietti LM-18 Computer Science SSI Embedded Systems I 9 Communication Lines (cont) SPI (cont) In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. –At CPOL=0 the base value of the clock is zero,i.e. the active state is 1 and idle state is 0. For CPHA=0, data are captured on the clock's rising edge (low→high transition) and data is output on a falling edge (high→low clock transition). For CPHA=1, data are captured on the clock's falling edge and data is output on a rising edge. –At CPOL=1 the base value of the clock is one (inversion of CPOL=0), i.e. the active state is 0 and idle state is 1. For CPHA=0, data are captured on clock's falling edge and data is output on a rising edge. For CPHA=1, data are captured on clock's rising edge and data is output on a falling edge.

©F.M. Rietti LM-18 Computer Science SSI Embedded Systems I 10 Communication Lines (cont) SPI (cont) –Advantages of SPI: It’s faster than asynchronous serial The receive hardware can be a simple shift register It supports multiple slaves –Disadvantages of SPI: It requires more signal lines (wires) than other communications methods The communications must be well-defined in advance (you can’t send random amounts of data whenever you want) The master must control all communications (slaves can’t talk directly to each other) It usually requires separate SS lines to each slave, which can be problematic if numerous slaves are needed.

©F.M. Rietti LM-18 Computer Science SSI Embedded Systems I 11 Communication Lines (cont) Arduino/Genuino SPI Library Link –Arduino SPI LibrayArduino SPI Libray