PRESENTATION Carry Look Ahead Adder.

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Presentation transcript:

PRESENTATION Carry Look Ahead Adder

Tayyaba Niazi. Saira Arshad. Sonia Saleem. Samra Farooq. Shifa Mohsin. Presenters: Tayyaba Niazi. Saira Arshad. Sonia Saleem. Samra Farooq. Shifa Mohsin.

What is carry look ahead adder? Definition:- “A carry-look ahead adder (CLA) is a type of fast parallel adder used in digital logic to calculate the carry signals in advance from the input signals.” They reduce carry propagation time and implement addition of binary numbers. It is also known as: Carry look ahead generator or fast adder or Carry predictor. It is an improvement over 'Ripple carry adder' circuit.

Inventor of Carry Look Ahead Adder Gerald Rosenberger of International Business Management first gave a patent of Carry Look Ahead Adders.

Circuit diagram of a 4-bit carry look ahead adder

SYMBOL CARRY (Input) A SUM B CARRY(Output)

Truth table of carry look ahead adder

Carry Look-Ahead Adder Design

Dependence of carry look ahead adder: Carry look ahead adder depends on two things : Calculating, for each digit position, whether that position is going to propagate a carry if one comes in from the right. Combining these calculated values to be able to deduce quickly whether, for each group of digits, that group is going to propagate a carry that comes in from the right.

The fact when carry will generate When both bits A and B are 1. When one of the two bits is 1 and the carry-in (carry of the previous stage) is 1.

Propagate & generate in carry look ahead adder Propagate P and Generate G in a carry look ahead adder is given by: Pi=Ai⊕Bi=…… (1) Gi =AiBi……….…(2)

Sum & carry generation in CLA Expressions for the output sum and the carry out are given by: Si=Pi⊕Ci…… (3) Ci=Gi + PiCi……(4)

Pi Si Ci-1 Ci+1 Gi

Carry outputs The Boolean expressions for carry outputs of various stages are: C1 = G0 + P0 . C0 C2 = G1 + G0 . P1 + C0 . P0 . P1 C3 = G2 + G1 . P2 + G0 . P1 . P2 + C0 . P0 . P1 . P2 C4 = G3 + G2 . P3 + G1 . P2 . P3 + G0 . P1 . P2 . P3 + C0 . P0 . P1 . P2 . P3

Implementation of 4-bit carry look ahead adder The carry look ahead 4-bit adder can also be used in a higher-level circuit by having each carry look ahead logic circuit produce a propagate and generate signal to a higher- level carry look ahead logic circuit. The group propagate (PG) and group generate (GG) for a 4-bit carry look ahead adder are : PG = P0 . P1 . P2 . P3 GG = G3 + G2 . P3 + G1 . P3 . P2 + G0 . P3 . P2 . P1

Construction of carry look ahead adder A 4 bit Carry Look Ahead adder can be constructed with the help of three steps : Generate All P and G internal signals. These can be generated simultaneously as C0 and all inputs are available. Output signals valid after 1τ. Generate all carry output signals (C1,C2,C3,C4). Output signals valid after 3τ. Generate sum signals S=Px or C. Output signals valid after 4τ.

Carry-look ahead adder ICs The high speed carry-look ahead adders are integrated on integrated circuits in different bit configurations . There are several individual carry generator ICs are available so that we have to make connection with logic gates to perform the addition operation.

A typical carry-look ahead generator IC is 74182 which accept four pairs of active low carry propagate ( as P0, P1, P2 and P3 ) and carry generate ( Go, G1, G2 and G3 ) signals and an active high input ( Cn ).

Advantages of carry look ahead adder 1. Like ripple carry adder we need not to wait for the propagation of carries to get the sum. 2. A carry-look ahead adder improves speed by reducing the amount of time required to determine carry bits. 3. The carry-look ahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger value bits.

Disadvantages of carry look ahead adder The disadvantage of CLA is that the carry logic block gets very complicated for more than 4-bits. For that reason, CLAs are usually implemented as 4-bit modules and are used in a hierarchical structure to realize adders that have multiples of 4-bits.