32ch Beam-Former for Medical Ultrasound Scanner Performed by : Alaa Mozlbat, Hanna Abo Hanna. Instructor : Evgeniy Kuksin.

Our Objective Build a switching module for ultrasound scanner. Our module

System Sync + config FPGA Probe Switch 192->32 Switch

Introduction Assuming this is a 192 channels screen, the switch has to scan it … … … 192 …

Scanner - Operation The Switch has to get 32 samples by a time, working as a shift scanner 12345… … … 192 … 12345… … … 192 … First Sampling:

Scanner The Switch has to get 32 samples by a time, working as a shift scanner Second Sampling: 12345… … … 192 …

Scanner The Switch has to get 32 samples by a time, working as a shift scanner Third Sampling: 12345… … … 192 …

MAX4968C This is the main device in the chip. The MAX4968C is a 16-channel,high linearity, high voltage analog Switch.

MAX4968C - Design Since MAX4968C is a 16 channel device, we create a 32 channel block by placing two of the MAX4968C by daisy-chaining connection. To cover 192 channels we use 6 blocks. The best way to build this system is by connecting these block by Daisy-chaining; daisy-chaining makes the control of the scanned channels much easier. The digital output from the shift register allows us to do so.

MAX4968C - Orcad

MAX4968C - OrCAD Design

Block Diagram DIN0 DOUT

Orcad Design

Functional diagram

Scanner Operation In the first 32 cycles we have to initialize the system with 32 ones (in DIN0). In the 32 nd cycle we should supply low LE in order to get the first sample. Afterwards, We will supply zeros and low LE in each sampling. The shift register with the Daisy-chaining will let the whole system to behave as a shift scanner.

Clock Splitter MAX4968C works in a maximal frequency of 25MHz. Single ended clock. The clock splitter we chose is PL123E-09 Low skew zero delay buffer of Micrel. The PL123E-09 works in frequencies of MHz. Requires 3.3V power input. The PL123E-09 has 8 outputs ( 2 banks of 4 outputs each).

Clock Splitter - Design Resistors, capacitors value has been chosen according to a simulation that was done. As mentioned before, the chip will contain 6 blocks, two clock wires are needed in each block. We use 6 out of the 8 outputs of the clock splitters, one for each block. (inside the block it can be split into two wires)

OrCAD Design – Clock Splitter

Simulation - SigXplorer

Regulators electronic device that maintains the voltage of a power source within acceptable limits. There are 2 types of regulators: Linear and Switching. The voltage regulator is needed to keep voltages within the prescribed range that can be tolerated by the electrical equipment using that voltage.

Linear Vs Switching SwitchingLinear Step up (boost), step down (buck), invertsOnly steps down (buck) so input voltage must be greater than output voltage Function High, except at very low load currents (μA), where switch- mode quiescent current (I Q ) is usually higher Low to medium, but actual battery life depends on load current and battery voltage over time. Efficiency is high if difference between input and output voltages is small Efficiency Low, as components usually run cool for power levels below 10 W High, if average load and/or input to output voltage difference are high Waste heat Medium to high, usually requiring inductor, diode, and filter caps in addition to the IC; for high-power circuits, external FETs are needed Low, usually requiring only the regulator and low-value bypass capacitors Complexity Larger than linear at low power, but smaller at power levels for which linear requires a heat sink Small to medium in portable designs, but may be larger if heat sinking is needed Size Medium to high, largely due to external components Low Total cost Medium to high, due to ripple at switching rate Low; no ripple, low noise, better noise rejection Ripple/Noise

Power Estimations Vdd CLK splitter Vpp Vdd Power needed: 12V *15mA*12 = 2.16W 3.3V *0.5mA*12 = 20mW 3.3V *90mA = 225mW Efficiency over 80% Power needed: ( )* 1.25=~ 0.320W Efficiency over 80% Power needed: (0.320)*1.25= 0.400W 12V source Power needed: = 3.1W Current needed: 3.1/12 = 0.26A We require 0.5A. 2.16W =~ 2.6W Vnn 200V *25uA*12 = 60mW (0.06)*1.25= 0.075W

Power Supply lmz21702ADP V5V 3.3V Ripple < 5mV, freq. =~ 2MHz PSRR =~ -45db (attenuation more than x1/150 – excellent) 5mV ripple /150 = 0.03mV

Power Supply – Orcad Design lmz21702ADP V5V 3.3V

Lmz21702 (DC/DC) – Orcad Design

Lmz SIMPLE SWITCHER (DC-DC) Ripple < 5mV, freq. =~ 2MHz

Orcad design – ADP7142

ADP Linear Regulator PSRR =~ -45db (attenuation more than x1/170 – excellent)

Orcad design – 12SM00S (12V -> n200V) Additional Capacitors

Orcad Design – System (1)

Orcad Design – System (2)

Orcad Design – System (3)

Signal Integrity – Power Supply Keep traces short. Long traces means transmission line, so without proper termination this will cause reflections. We place decoupling capacitors as close as possible to the VDD pins to limit noise from the power supply. We add a ferrite bead in series with VDD to help prevent noise from other board sources.

Summary 1. great learning experience 2. Digital and Analog circuits. 3. Orcad Design. 4. Solutions for signal integrity problems. 5. Packages. 6. Choosing Regulators ( LDO && DC/DC ). 7. Simulation tools – SigXplore. 8. High Frequency System-Design.

“CHAPTER 12: PRINTED CIRCUIT BOARD (PCB) DESIGN ISSUES” 4-“Decoupling Techniques “ 5- “PCB Design” 6-