P. Name Nikhef Amsterdam Electronics- Technology Vladimir Gromov, NIKHEF, Amsterdam. GOSSIPO-3 Meeting May 25, Layout of the Front-end

P. Name Nikhef Amsterdam Electronics- Technology Progress Problem Plans (May 25, 2009) GOSSIPO-3 Meeting 25/05/2009 V. Gromov 2 Progress: - a new design kit has been stated at NIKHEF Virtuoso IC sch & symbol of preamp_comp_g3 cell is checked_in NikhefWork lib -.sch & symbol of bias_g3 is checked_in NikhefWork lib. - pre-design of the layout of the cells Problems: - metallization option of V DM version: FE-I4 : Mosis (20 July submit) : Triple-well NFET’s : T3 or PI options - poly-resistor: OP P+ poly OP RP PC poly Plans: - final list of the cell to be submitted / person responsible / time schedule - layout + extraction + verification + correction + layout …..

P. Name Nikhef Amsterdam Electronics- Technology T3 process (a quesswork) P-well P+ N-well N+ (T3 layer) P (BT layer) BT block (IBLK layer) connection N+ GOSSIPO-3 Meeting 02/06/2009 V. Gromov 3

P. Name Nikhef Amsterdam Electronics- Technology Progress Problem Plans (June 2, 2009) Progress: - BEOL_STACK (MA 3_2_3) has been confirmed for the submit ( Mosis, July 20) - preliminary layout of the preamp_comp_g3 cell is checked_in NikhefWork lib (DRC is OK!) - extraction with parasitic caps is done, analysis of the PCAPS at critical nodes is done - ways to improve the layout have been proposed - results of simulations with av_extracted view have been compared to those with.sch view - specification as well as preliminary.sch view of the ingride preamp is done. Problems: - it is still to decide on T3 or PI options - poly-resistor: OP P+ poly OP RP PC poly - extraction of the NFETTW does not work properly in preamp_comp_g3 cell, therefore LVS does not match. - many improvements are needed in the layout of preamp_comp_g3 cell in order to reduce PCAPS. Plans: - I assume Andre will finalize layout of the preamp_comp_g3 cell - I will take on ingride_preamp, threshold_DAC and TDC_oscillator cells. GOSSIPO-3 Meeting 02/06/2009 V. Gromov 4

P. Name Nikhef Amsterdam Electronics- Technology DM (MA) version: BEOL_STACK_3_2_3 STI (0.35) PC wire (0.15) PC gate M1 (0.29) Copper CA (0.35) Mx (x=2,3) (0.32) Copper Vx (x=1,2) (0.35 VL (0.65) MQ (0.55) Copper Kx (resistor) VQ (0.65) MG (0.55) Copper FY (1.4) LY (0.46) ALU QY MIM E1 (3.0) Copper FT (4.0) MA (4.0) ALU F1 (4.0) L1 (resistor) Oxide (1.35) Nitride (0.45) Polyimide (2.5) from 1um to 7um over MA Polyimide LV (C4 bumpbond) DV (wirebond) GOSSIPO-3 Meeting 02/06/2009 V. Gromov 5

P. Name Nikhef Amsterdam Electronics- Technology Input connection layout 22um Input pad MA+LV layers Test bus E1 layer Ctest-to-in = 1.3fF Cin-to-sub = 5fF GOSSIPO-3 Meeting 02/06/2009 V. Gromov 6

P. Name Nikhef Amsterdam Electronics- Technology Metal-to-metal capacitor Mimcap: Area capacitance 2.05 fF / um 2 Perimeter capacitance fF / um LY (0.46) ALU FT QY MIM E1 (3.0) Copper FT Vias GOSSIPO-3 Meeting 02/06/2009 V. Gromov 7

P. Name Nikhef Amsterdam Electronics- Technology preamp_comp_g3 cell (symbol view) Nominal voltage at the pin Current driven in/out of the pin (both DC and AC) GOSSIPO-3 Meeting 02/06/2009 V. Gromov 8

P. Name Nikhef Amsterdam Electronics- Technology preamp_comp_g3 cell (schematic view) Parasitic capacitances at these critical nodes are to be closely watched In_preamp out_fb AB C GOSSIPO-3 Meeting 02/06/2009 V. Gromov 9

P. Name Nikhef Amsterdam Electronics- Technology mimcap input pad 28um 20um !!! This preliminary layout is meant to estimate the cell’s area and check on the major problems. !!! In the multi-wells design a lot of area is taken by clearances between the wells. !!! Still in-well-layout should be made much more dense by means of sharing of diffusion regions and poly lines. preamp_comp_g3 cell (layout view) GOSSIPO-3 Meeting 02/06/2009 V. Gromov 10

P. Name Nikhef Amsterdam Electronics- Technology preamp_comp_g3 cell (av_extracted view) !!! ERROR: Most of the triple-well fets (nfettw) are extracted as standard nfets. Parasitic capacitance caused by the wiring: IBM_PDK → Query → Selected Nets PCAP / C-total in_preamp: C total=7fF (expected 3fF), Csub=5fF, Cin_preamp_test = 1.3fF (test cap), Cout_preamp = 0.8fF (feedback cap → gain↓, expected 0fF) consider shielding of the input pad / attached vias, space separation between input pad and the mimcap’s vias. out_fb: C total=0.14fF (very good !!!) A: C total=4.2fF (internal fet’s capacitance is 4fF → reduces open loop bandwidth of the preamp) rearrange placement of the nfet’s and the pfet’s, put them as close as possible, reduce length of the connections. B: C total=1.6fF (internal fet’s capacitance is 2.2fF → slows down response of the comparator) C: C total= 1.8fF → slows down response of the comparator !!! Think how to arrange Vdd, gnd and bias buses for a COLOUMN of the pixel in order to reduce parasitic coupling to the critical nodes. !!! After running FLOATING WELLS / METALS checks, and ANTENA checks there will be a number of tie-downs required. Those will add capacitance to the circuit. Run these checks (together with chip_ring and bondpads with ESD protection) before drawing final layout. GOSSIPO-3 Meeting 02/06/2009 V. Gromov 11

P. Name Nikhef Amsterdam Electronics- Technology Simulation with preamp_comp_g3 cell Schematic view ∆Uin=46mV Cin=1.3fF, Qin=60aC (375e - ) Cpar=5.7fF Uout_preamp = 60mV Preamp_rise time= 10ns Schematic view ∆Uin=460mV Cin=1.3fF, Qin=600aC (3750e - ) Cpar=5.7fF Comp_delay = 3.6ns Av_extracted view ∆Uin=46mV Cin=1.3fF (internal), Qin=60aC (375e - ) Uout_preamp = 28mV Preamp_rise time= 10ns Av_extracted view ∆Uin=460mV Cin=1.3fF (internal), Qin=6000aC (3750e - ) Comp_delay = 5.5ns TEST BENCH : Preamp_test_bench_23_05_09.sch larger Cfb + parasitic caps parasitic caps GOSSIPO-3 Meeting 02/06/2009 V. Gromov 12

P. Name Nikhef Amsterdam Electronics- Technology GOSSIPO-3 chip : work partitioning Part+StatusWorkdesignlayoutDesigners PreampschematicDesign, simulation, implementation in progress Andre(+Vlad) DiscriminatorschematicDesign, simulation, implementation in progress Andre(+Vlad) Threshold DAC/opampschematic doneto be made Vladimir TDC oscillatorPresent designStability- and uniformity optimization to be made Vlad + Sinan Power distribution + regulator design schematicDesign, simulation, implementation??? Chris. B TDC & countersschematic ok in progress Sinan + Vlad ReadoutcheckNew design??? Nikhef (Ruud) Bias blocks???New design in progress to be made Andre(+Vlad) I/O pads & buffersSome of gossipo2Copy ???? share Analog output buffer (voltage follower) --Design, simulation, implementation done Andre(+Vlad) INGRID preamp ?RequestedNew item: specify & design donealmost done Vladimir Chip integration--Full chip assembly & verification??? Nikhef (Ruud) Driver for the comp (a chain of inverters) NeededFull chip assembly & verification done Andre(+Vlad) GOSSIPO-3 Meeting 02/06/2009 V. Gromov 13

P. Name Nikhef Amsterdam Electronics- Technology gossipo3 Preamp discr bias Buf LDO bias TDC&ToT THR in test 6 bias 4x contr Aout Dout Osc_out VoutVin 2x bias clk & read Tout VddLDO VddProt VddD The pad color identifies the ESD coupling power The pad color identifies the ESD coupling power VddAna GNDProt GNDAna Driver GOSSIPO-3 Meeting 02/06/2009 V. Gromov 14

P. Name Nikhef Amsterdam Electronics- Technology INGRID preamp (inputs for design) A: Full reticle chip (1.4cm x 1.4cm) Cpar = 35.2pF ( huge cap ) = 8.8pF/m● 2cm 2 / 50μm () GOSSIPO mm x 1.76mm) Cpar = 0.55pF = 8.8pF/m● 3.1mm 2 / 50μm Cpar ≈ 2pF ( reasonable cap ) Cbond_wire ≈ 1pf B: Signal size (Positive Polarity): 0… electrons Charge, electrons p(n), Entries Gas gain =2000 Gas gain = 4000 Gas gain =8000 GOSSIPO-3 Meeting 02/06/2009 V. Gromov 15

P. Name Nikhef Amsterdam Electronics- Technology Progress Problem Plans (June 9, 2009) Progress: - T3 option will not be supported in the tape-out (July 20) - all NFETTW’s must be placed in PI region - poly-resistor: OP P+ poly will be supported both in the tape-out (July 20) and future FE-I4 submit → present Bandgap Ref. Circuit could be integrated on the chip - extraction of the NFETTW does work properly in ASSURA when LVS.dr1 layer in on. - buf_ana and driver cells have been made (.sch, sym, layout + verification + re-simulation with parasitic) - preamp_ingrid cell is almost ready Problems: - RCX extraction work unpredictable. - choice of the decoupling capacitor in the preamp_comp_g3 block is to be made Plans: - I will finish on preamp_ingrid block and take on threshold_DAC and TDC_oscillator cells. - next week all the individual blocks should be ready for the on-chip integration GOSSIPO-3 Meeting 09/06/2009 V. Gromov 16

P. Name Nikhef Amsterdam Electronics- Technology INGRID preamp (the cell) Size : 100μm x 60μm Power supply voltage/ current: 1.2V /1.24mA Capable to drive probe (Cout = 8pF) Capable to operate with Cin= 0…2pF On-cell test cap ( parasitic fringe MA,E1,LY ): 20fF Feedback cap (VNCAP) : 20fF Dynamic range: 0… e - (1.1V…0.56V) Noise: σ = 1mv (250 e - ) Rise time: 130ns Decay time: 5 μsec Open loop gain (dc): 50dB Phase Margin: 100° GOSSIPO-3 Meeting 16/06/2009 V. Gromov 17

P. Name Nikhef Amsterdam Electronics- Technology INGRID preamp (preamp_ingrid_15_06_09) Bond pads required for: bias1, biasPC5, bias_fb1, biasPC6, out_preamp_buf, preamp_in_test, vdd_preamp, gnd_ana, subcon GOSSIPO-3 Meeting 16/06/2009 V. Gromov 18

P. Name Nikhef Amsterdam Electronics- Technology AC-coupling in the preamp_comp cell Mimcap (too much area, parasitic coupling) Present solution (preamp_comp_g3) Improved solution (preamp_comp_g3_1) NCAP (not much area 4μm x 4μm) discharge circuit (does not distort the signal ) discharge circuit (does not work properly, distorts the signal ) GOSSIPO-3 Meeting 16/06/2009 V. Gromov 19

P. Name Nikhef Amsterdam Electronics- Technology Decoupling capacitor choice. ! GOSSIPO-3 Meeting 16/06/2009 V. Gromov 20

P. Name Nikhef Amsterdam Electronics- Technology Performance of the comparator (preamp_comp_g3) Ideal step voltage signal at the input Uthr = 40mV Signals 1● 50mV = 50mV Internal delay 5.5ns 2● 50mV = 100mV 2.4ns 4● 50mV = 200mV 1.9ns 10 ● 50mV = 500mV 0.8ns 16● 50mV = 800mV 0.5ns Uout(t) !!! Internal delay is about 1.6ns when size of the signal is 10 times larger than the threshold. !!! Statistical spread of the Int. delay is ±0.5ns (mismatch only) !!! Sensitivities: Signal = 500mV (10 times the threshold) ∆Delay/∆Vdd = ∆61ps / ∆100mV, ∆Delay/∆Ibias = ∆9.1ps / ∆100nA when Ibias ≥ 0.9μA !!! Input referred statistical spread σ = 17mV (110e - ) = 5.6mV ●√ 2/ √ (W ● L) = 0.24μm = 0.9μm Internal delay vs input signal size Present solution (preamp_comp_g3) GOSSIPO-3 Meeting 16/06/2009 V. Gromov 21

P. Name Nikhef Amsterdam Electronics- Technology Signals 1● 375e - = 375e - Internal delay 9.2ns 2● 375e - = 750e - 5.6ns 4● 375e - = 1.5ke - 4.3ns 10 ● 375e - = 3.75ke - 3.4ns 16● 375e - = 6ke ns Uthr = 40mV !!! Internal delay is about 3.4ns when size of the signal is 10 times larger than the threshold. Comparator + preamplifier (preamp_comp_g3) Internal delay vs size of the input δ- pulse current Preamp out: time-to-threshold Signals 1● 375e - = 375e - TtT 4.0ns 2● 375e - = 750e - 2.4ns 4● 375e - = 1.5ke - 1.7ns 10 ● 375e - = 3.75ke - 1.4ns 16● 375e - = 6ke - 1.4ns Present solution (preamp_comp_g3) GOSSIPO-3 Meeting 16/06/2009 V. Gromov 22

P. Name Nikhef Amsterdam Electronics- Technology GOSSIPO-3 Meeting 16/06/2009 V. Gromov 23 Progress Problem Plans (June 16, 2009) Progress: - ingrid_preamp block is done - analysis on the choice of the coupling cap in preamp_comp block has been carried out - NCAP seems to be a suitable candidate (more detailed simulations needed to verify, see cell preamp_comp_g3_1 in the repository ) - base line recovery circuit at the input of the comparator does not operate properly at large signals (distorts the shape of the signal, see cell preamp_comp_g3 in the repository) - a new solution have been proposed (more detailed simulations needed to verify, see cell preamp_comp_g3_1 in the repository ) Problems: - we are far behind the schedule (all individual blocks ready this week) - antenna, floating wells, ESD …and other advanced DRC checks have not been done on the new-designed blocks Plans: - I will take on threshold_DAC and TDC_oscillator blocks - next week all the individual blocks should be ready for the on-chip integration ????

P. Name Nikhef Amsterdam Electronics- Technology Threshold DAC (thr_dac_test_bench_19_06_09) Bond pads required for: THR_bias, out, a0, b0, c0, d0. bias_g3dac_voltage_genswitch_tree dac_decoder On-pixel part 18μm x 2.5μm GOSSIPO-3 Meeting 25/06/2009 V. Gromov 24

P. Name Nikhef Amsterdam Electronics- Technology Oscillator block Oscillator inverters powered by vdd_osc (0.64V…1.1V) Gates powered by vdd_dig=1.2V Coexistence of 1.2V logic domain and 0.64V logic domain. GOSSIPO-3 Meeting 25/06/2009 V. Gromov 25 Level shifter (40μA extra current in the time of oscillation activity)

P. Name Nikhef Amsterdam Electronics- Technology Oscillator circuit. Output signal at various process corners and power supply voltages. vdd_osc=0.85V nominal corner (case=1) vdd_osc=0.85V fast corner (case=6) vdd_osc=0.85V slow corner (case=7) vdd_osc=0.85V nominal corner (case=1) vdd_osc=0.64V fast corner (case=6) vdd_osc=1.1V slow corner (case=7) GOSSIPO-3 Meeting 25/06/2009 V. Gromov 26 T osc ideal = 1.724ns A: case =7, Temp=80°C, vdd_osc=1.1V T osc slow = 1.752ns B: case =6, Temp=27°C, vdd_osc=0.612V T osc fast = 1.733ns C: case = 1, Temp=27°C, vdd_osc=0.76V T osc nom = 1.73ns

P. Name Nikhef Amsterdam Electronics- Technology Ideal oscillation frequency en_osc start_oscstop_osc out_osc 25ns (max) Final State of the Counter State = 14 (max for LFSR) delay fb delay fb = 25ns/29 = 0.862ns → T osc ideal = 2 ● delay fb = 1.724ns arrival time of the stop_osc signal T osc ideal GOSSIPO-3 Meeting 25/06/2009 V. Gromov 27

P. Name Nikhef Amsterdam Electronics- Technology Operation of the oscillator block en_osc start stop out_osc state “0” out_osc state “1” stop out_osc state “1” stop out_osc state “2” stop out_osc state “2” stop Counter clock GOSSIPO-3 Meeting 25/06/2009 V. Gromov 28

P. Name Nikhef Amsterdam Electronics- Technology Oscillator block: time diagrams. net_A net_B net_C net_D stop_osc start_osc out_osc 25ns (max) clk +125ps ?? stop_osc start_osc +60ps net_A net_D net_B +60ps +820ps +120ps net_C out_osc +60ps GOSSIPO-3 Meeting 25/06/2009 V. Gromov 29

P. Name Nikhef Amsterdam Electronics- Technology Progress Problem Plans (June 23, 2009) Progress: - all the blocks needed for the threshold DAC are done. - the on-chip block (switch_tree) measures 18μm x 2.5μm - in the future, the configuration memory (4bits) will also take the pixel’s area. - size of the delay cells in the oscillator block have been adjusted in order to be able to equalize oscillation frequency between all the process corners within the power supply voltage range provided by the LDO (0.64V…1.1V) - a level shifter circuit have been designed in order to interface between the 1.2V logic domain and the 0.64V logic domain. - power consumption of the level_shifter circuit has been evaluated in all process corners. Problems: - we are far behind the schedule (all individual blocks ready previous week) - we should decide on the shift of the tape-out date to September 20. Plans: - continue layouting and verification of the TDC related blocks. - start integration of the individual blocks on the chip. GOSSIPO-3 Meeting 25/06/2009 V. Gromov 30

P. Name Nikhef Amsterdam Electronics- Technology Schematic of the LDO ??? W=2mm !!!! W=48mm GOSSIPO-3 Meeting 30/06/2009 V. Gromov 31

P. Name Nikhef Amsterdam Electronics- Technology Bias block Generates bias voltages (currents) for all the blocks. GOSSIPO-3 Meeting 30/06/2009 V. Gromov 32

P. Name Nikhef Amsterdam Electronics- Technology GOSSIPO-3 Meeting 30/06/2009 V. Gromov 33 Progress Problem Plans (June 30, 2009) Progress: - schematic view of bias_g3 block is done - schematic view of oscillator block is verified, the layout is being drawn Problems: - place & routing of the TDC block is not going smooth. - test benches for the TDC-related blocks need to be made. Plans: - continue layouting and verification of the TDC related blocks.