First Thermal Estimates for Serial Powering at Chip/Module Level Yadira Padilla Joe Conway, Charlie Strohman, Jim Alexander, Anders Ryd, Julia Thom Cornell University Jorgen Christiansen CERN July 21, 2016

Outline Shunt and LDO power dissipation thermal issues Chip and Dee Geometry Assumptions and Thermal properties Nominal Case: Operation Max case (1.5X): Operation Worst case (1.5X): Shut down Summary and comments 7/21/20162

Shunt and LDO power dissipation thermal issues 7/21/20163

Shunt-LDO power dissipation Nominal operation average IC current: 2 x 0.8A (analog and 1.2v – What if this can become 2x Start-up Mis-configuration SEU Needs to inject enough current to get system started – What if this can become 0. Powering down analog FEs No clock to digital All power will have to be “burned” by SLDO Nominal shunt current: ~25% – Total current ~2 x 1A – Note: This is what allows serial power to run with constant currents despite load variations LDO minimum voltage: 1A (lower would be nice) – Depends on current Optimizing injected current (controller by external PS) – Must assure correct function in all cases and no “melt-down” – Can be adjusted on-line Optimizing Shunt-LDO (SLDO): – Resistance (defined by on-module resistor and possibly on-line) 4

Shunt-LDO regulator Classical shunt regulator: Inject current into voltage “clamps”/shunts + LDO Problematic current sharing: Variations in clamp voltages and parasitic resistance Coupling between analog and digital supply voltage via common shunt ATLAS outer tracker developed different schemes to cope with this but this work is now abandoned (decided for DC/DC power) 5 Resistive SLDO: Make it look like well controlled resistors Well defined current sharing between resistors Multiple “independent” shunt-LDOs per chip with different output voltages Multiple chips in parallel Improved decoupling between analog and digital (Increased power losses) How to make shunt-LDO appear resistive ? Optimal: Compromise between the two ? ~4 chips per module

Thermal issues Pixel array: 1.7cm x 1.7cm, ~uniform analog and digital power – Nominal operation power: 1.445W ( W digital W Analog) – Maximum: 2.023W – Minimum power: 0W 0.5A shunt-LDO building block – Shunt (NMOS): 5 transistors of 130µm x 30µm = 650um x 30um (yellow) – LDO (PMOS): 5 transistors of 85µmx30µm = 425um x 30um (red) – Power dissipated in thin top layer of Si (few um). Shunt-LDO’s at bottom of chip – Analog: 4 blocks of 0.5A = Max 2A – Digital: 4 blocks of 0.5A = Max 2A – Interleaved to have better heat distribution – (we may even be forced to distribute this within the pixel array in case of serious thermal problems) Heat removal from back side of pixel chip (initially forget about bump bonded sensor on top) – Initial trial with uniform heat removal across whole chip – Cooling tube below shunt-LDOs + cooling tube middle pixel array with some kind of heat distribution layer in-between 6

Chip and Dee Geometry 7/21/20167

Chip and dee geometry 8 Each Z-layer consists of 2 Dees, one with the 1 st and 3 rd rings of modules (Odd Dee) and the other with the 2 nd and 4 th rings (Even Dee) The Dees are carbon fiber(CF) sandwich structures with CO 2 cooling tubes embedded in thermally conductive foam with CF face sheets on either side Pixel modules are populated on both sides of the Dee to create a hermetic layer The Dees will also host the LpGBTs and other electrical accessories in high-radius locations Small Disc Even Dee Odd Dee Pixel chip Si Sensor HDI

Thermophysical properties CO 2 Refrigerant Temperature = -30 o C Heat transfer coefficient = 5000 W/m 2 -K Conductive Thermal Pathways Thermal Conductivity [W/m-K] Characteristic Length [mm] ROC, Shunt, LDO Silicon Phase Change Glue Laird Film Carbon Fiber Tencate K13C2V Permanent Glue 3M Carbon Foam Allcomp K Thermal Grease TC Tube Stainless steel

Power “distribution” on chip Shunt-LDOs: Worst case Max power: 6.6W (Max power: 2.023W) Nominal power: 1.445W Min power: 0W Pixel array 17 mm X 17mm ~19mm

Model assumptions Convert conductivity for thermal grease and glues into a thermal conductance value between contact regions so that glues and films are not modeled as solid objects – h Laird film = W/mm 2 -K – h 3M2216 = W/mm 2 -K – h TC5022 = W/mm 2 -K Use constant heat transfer coefficient and constant temperature for CO 2 Thermophysical properties are homogenous throughout each body and not temperature dependent All heat is transferred to CO 2 refrigerant One half of a Dee ring will be analyzed Uniform analog and digital power LDO, Shunt dissipation does not change with pixel array size (same for 20mm 2 and 17mm 2

Nominal case: Operation 7/21/201612

Nominal case: operation Pixel array: 2 W*(172/202)=1.445 W – Uniformly distributed over pixel array of 17x17 mm Analog shunt-LDO: 0.5 W – 4 shunts each burning 0.2 W/4 = 0.05 W – 4 LDOs each burning: 0.3 W/4 = W Digital shunt-LDO: 0.5 W – 4 shunts each burning 0.2 W/4 = 0.05 W – 4 LDOs each burning: 0.3 W/4 = W Total power per chip W Thermal issues (Total power W): 1.Temperature gradient over array less than ~5 o C Analog front-ends quite temperature sensitive. Acceptable gradient to be verified with circuit simulations) 2.Hottest spot on chip (shunt-LDO) temperature 13

Nominal case: results Resistance due to glues keeps heat on chip increasing temps on chip Temp distribution on pixel array dependent on cooling line position Conclusion: Hottest spot on LDO (Below 1,414 o C melting point of silicon), ΔT of pixel array about 2.5 o C 7/21/ LocationΔT [ o C] Quarter D10.5 ROC Pixel area2.5 LDO, Shunt, Periphery3.7 Max Temperature o C Min Temperature o C

Max case (1.5x): Operation 7/21/201615

Max case (1.5xnominal power): operation Pixel array: W (When power-up or if mis-configured) – Uniformly distributed over pixel array of 17x17 mm Analog shunt-LDO: 1.9 W – 4 shunts each burning 0.4 W/4 = 0.1 W – 4 LDOs each burning: 1.5 W/4 = W Digital shunt-LDO: 1.9 W – 4 shunts each burning 0.4 W/4 = 0.05 W – 4 LDOs each burning: 1.5 W/4 = W Total power W. Thermal issues (Power W): – Pixel chip does not need to be operational but it must be guaranteed that the chip does not “melt” – Hottest spot on chip (shunt-LDO) temperature 16

Max case (1.5xnominal power): results Temperatures much higher in chip due to higher loads by the shunts and LDOs Resistance of glues is still an issue Conclusion: Hottest spot on LDO 2.6 o C (Below 1,414 o C melting point of silicon), ΔT of pixel array about 2.5 o C 7/21/ LocationΔT [ o C] Quarter D31.0 ROC Pixel area6.9 LDO, Shunt, Periphery17.0 Max Temperature2.57 o C Min Temperature o C

Worst case (1.5x): shut-down 7/21/201618

Worst case (1.5x): shut-down Pixel array: 0 W (Pixel array shut-down. Power dissipated by on-chip shunt) – Uniformly distributed over pixel array of 17x17mm Analog shunt-LDO: 3.3 W – 4 shunts each burning 1.8 W/4 = 0.45 W – 4 LDOs each burning: 1.5 W/4 = W Digital shunt-LDO: 3.3 W – 4 shunts each burning 1.8 W/4 = 0.45 W – 4 LDOs each burning: 1.5 W/4 = W Total power 6.6 W Thermal issues (413.9 W): – Hottest spots on chip (shunt or LDO) temperature Chip should not “melt” Thermal induced bending of module Other ? 19

Worst case: results Temperatures much higher in chip due to higher loads by the shunts and LDOsTemp distribution on pixel array dependent on cooling line position Conclusion: Hottest spot on LDO o C (Below 1,414 o C melting point of silicon), ΔT of pixel array about 5.1 o C 7/21/ LocationΔT [ o C] Quarter D44.4 ROC Pixel area5.1 LDO, Shunt, Periphery26.0 Max Temperature16.77 o C Min Temperature o C

Scenario: normal > normal X1.5 > shutdown 7/21/ Nominal case Nominal case X1.5 Worst case o C o C Failure would not cause chips to melt

Glue and thermal grease effect Assuming worst case scenario with heat loads Assuming a perfect world, no glue or thermal resistance from thermal grease Highest temperature achievable would be 2.74 o C (16.77 o C if thermal resistance due to glue and grease) due to better temperature distribution 7/21/201622

Comments and Conclusions 7/21/201623

Comments and pending questions Chips will not melt even at worst case Material selection key to thermal dissipation Resistances due to proper contact (glue and thermal grease) key in removing heat from LDO and shunts; still limited by properties of remaining materials More detailed analysis needed as chip design and Dee materials are finalized Thermal analysis on chip will move to Andy Jung from Purdue University, with Cornell as secondary check 7/21/201624

Thank you! 7/21/201625

Additional slide: Thermal loads applied 7/21/ PowerAreaHeat Flux [W/mm 2 ] Nominal Pix array Analog Shunts Analog LDO Digital Shunt Digital LDO PowerAreaHeat Flux [W/mm2] Nominal X 1.5 Pix array Analog Shunts Analog LDO Digital Shunt Digital LDO PowerAreaHeat Flux [W/mm2] Worst case Pix array Analog Shunts Analog LDO Digital Shunt Digital LDO CO 2 Refrigerant Temperature = -30 o C Heat transfer coefficient = 5000 W/m 2 -K h Laird film = W/mm 2 -K h 3M2216 = W/mm 2 -K h TC5022 = W/mm 2 -K