R. Kluit Nikhef Amsterdam R. Kluit Nikhef Amsterdam Gossipo3 3 rd Prototype of a front-end chip for 3D MPGD 1/27/20091GOSSIPO3 prototype

R. Kluit Nikhef Amsterdam R. Kluit Nikhef Amsterdam Requirements for Front-End Good efficiency for 1000e - input signals : Noise <100e - rms. Fast input for accurate drift time determination: ~1-2ns resolution => peaking time ~30ns. Low power for high resolution: Goal 100mW/cm 2, with 55 µm pixels => 3 µW/pixel Need Preamp, Discriminator, TDC (4b), ToT (4b), Buffers, Configuration (e.g. Threshold DAC) and test for each pixel. For SLHC design (future): Bunch & Event identification More (2?) event buffers per pixel Serial communication & Trigger handling High speed serial readout (>Gb/s), ATLAS compatible. 1/27/20092GOSSIPO3 prototype

R. Kluit Nikhef Amsterdam R. Kluit Nikhef Amsterdam Pixel size : => 55 x 55 μ m cell size Sens. Area:=> 1.76 x 1.76 mm => 32 x 32 aktive Pixels ~540 μ m space between matrix and edge chip Dyke 4 rows of terminating (empty) pixels; total array: 40x40 pixels Chip size ~ 3.5 x 3.9 mm = 13.6 mm 2 (10.5 mm 2 ~$48 k in MOSIS) Need some (3) analogue pixel outputs on edge matrix Study the ion drift and pulse shape (add analog output buffers) Area available outside pixel array for other test structures: Preamp, Discriminator, TDC, Bias, ….. Test different pixel options (e.g. preamp, oscillator, …..) Chip size & pixels 1/27/2009GOSSIPO3 prototype3

R. Kluit Nikhef Amsterdam Gossipo3 (1) 1/27/2009GOSSIPO3 prototype4 In each pixel: -Preamp & Discriminator -Threshold DAC + reg. -TDC 4bit, 1.7 ns bins -ToT 4bit, 25ns bins -Read Latency counter, 4bit (400ns) or 12bit (100us) -Hit overflow detection ? (1bit) Readout data: = 21 bits/pixel (?) Self trigger/Fast-OR Test Pulse injection Mask.... Timed readout, variable latency Readout all pixels Buffer/pixel, auto clear after latency, add multi-hit flag. Readout speed 40MHz, 4/8 bits bus ?

R. Kluit Nikhef Amsterdam R. Kluit Nikhef Amsterdam Do not design for Radiation tolerance (yet, but keep in mind). Low power design => Goal 100mW/cm 2, => 55x55um pixels Simple readout, shift all 4/8 bit bus. Simple Chip Configuration, shift in. Add bandgap reference for bias (option) Gossipo3 (2) 1/27/20095GOSSIPO3 prototype

R. Kluit Nikhef Amsterdam Additional prototype Agreed Proposal: Before Gossipo3 submission (~12mm 2 ), test basic circuits in intermediate prototype: Preamp (with bias) Discriminator (with bias) TDC/oscillator ? other features ? MOSIS MPW’s: May 11 th, prefer July 20 th Name Gossipo3.0 &..3.1, OR Gossipo3 & Gossipo4 ? 1/27/2009GOSSIPO3 prototype6

R. Kluit Nikhef Amsterdam Time Scale Time scale Gossipo3.1: 2009: -Spec & feasibility …May -design …Sept -tape-out Nov. 2010: -Chip test March- May -Detector processing …. -Beam test Aug-Oct? Time scale Gossipo3.0: 2009: prototype chip with basic circuits: -preamp -discriminator -oscillator (tuned?) -TDC ? Goal: Tape-out July 11 th. 1/27/2009GOSSIPO3 prototype7

R. Kluit Nikhef Amsterdam R. Kluit Nikhef Amsterdam Define IBM 130nm Technology options, LM/DM. (to be defined, RK) and IBM design kit version Agreed Proposal: Main engineer: V. Gromov. Global chip design by Nikhef. Blocks by Nikhef & Bonn. Discuss in weekly meeting, Tuesdays 15:00. Use Bonn test environment, will be adapted to Gossipo3 (Bonn) Some gossipo2 chips available for test (oscillator) in Bonn. Decide week 6 if useful for measurements. Set up design repository as with FE-I4 design group. (Ruud) Discuss if INGRID preamp is necessary (Vladimir, Harry) Provide Bonn with information about the oscillator and preamp (Vladimir) General issues 1/27/2009GOSSIPO3 prototype8

R. Kluit Nikhef Amsterdam Part+StatusWorkdesignlayoutDesigners PreampConcept designDesign, simulation, implementationAndre+Vlad DiscriminatorConcept designt.b.d. Threshold DAC/opampIdeat.b.d. TDC oscillatorPresent designStability and uniformity optimizationAndre +C TDC & countersConcept designNikhef Fast-ORplanNikhef ReadoutLike gossipo2Nikhef Bias blocks0New designt.b.d. I/O pads & buffersSome of gossipo2Copy ? Signal distribution/buffers 0Nikhef(?) Power distribution analysis (TDC) planSee TDC oscillatorBonn (?) INGRID preamp ?Necessity ?New item: specify & feasibility & design Chip integration--Full chip assembly & verificationNikhef Work partitioning (preliminary) 1/27/2009GOSSIPO3 prototype9

R. Kluit Nikhef Amsterdam R. Kluit Nikhef Amsterdam Need more specifications on: Input signal charge (distribution), required threshold spread, gain,… (Harry) Test pulse feature ? INGRID preamp, feasibility, specs (Harry) … Next meeting (week 6): Chip floorplan Work sharing; Bonn preamp, oscillator (+power), ? Design ideas/proposals, analog & readout (chip functionality) Design repository, Design kit. Intermediate prototype Test Bonn ? Next 1/27/2009GOSSIPO3 prototype10