IC Design Research Laboratory Dr. George L. Engel Department of Electrical and Computer Engineering Southern Illinois University Edwardsville 1 A Case Study: Design of a CMOS ASIC For Pulse Shape Discrimination ANSiP Acireale, Italy November 21 – 24, 2011

IC Design Research Laboratory Introduction 2 This talk will discuss the design flow of a CMOS ASIC (Application Specific Integrated Circuit), from modeling of the integrated circuit (IC) at the system level to tapeout. The presentation will be in the form of a case study.

IC Design Research Laboratory Design Conception Physicists identify need for ASIC Physicists describe how IC is to operate. Physicists describe how IC will be used in a larger system. IC designers determine appropriate technology and obtain Cadence process design kit (PDK) from foundry.

IC Design Research Laboratory The Team Southern Illinois University Edwardsville: Dr. George Engel (professor / analog designer) Michael Hall (graduate student / behavioral simulation / system designer) Justin Proctor (graduate student / electrical simulation) Dinesh Dasari (graduate student / analog layout ) Nagendra Sai Valluru (graduate student / digital layout) Washington University in St. Louis: Dr. Lee Sobotka (professor / project manager / CEO / CFO) Jon Elson (electronics specialist) Dr. Robert Charity (researcher / end-user) Rebecca Shane (graduate student / test engineer)

IC Design Research Laboratory Pulse Shape Discrimination

IC Design Research Laboratory Phases of Development  Top-Down System Level Design and Verification  Electrical Level Design and Verification  Physical Layout and Verification  Final Design Verification and Tapeout  Fabrication  Integration into a System  Testing of Prototype System

IC Design Research Laboratory System Level Design (Top-Down)

IC Design Research Laboratory Electrical-Level Design (Bottom-Up)

IC Design Research Laboratory Physical Layout

IC Design Research Laboratory Final Verification and Tapeout

IC Design Research Laboratory The ASIC!

IC Design Research Laboratory Integration Into a System

IC Design Research Laboratory Prototype Testing Pulse Shape Discrimination Total pulse height information.

IC Design Research Laboratory Questions 14 ???

IC Design Research Laboratory Timing permitting ….

IC Design Research Laboratory Op Amp Used in Integrator

IC Design Research Laboratory Use of MathCAD®

IC Design Research Laboratory Use of MathCAD®

IC Design Research Laboratory Excel Datasheet

IC Design Research Laboratory VerilogA (Op Amp) module ota(vout, vref, vin_p, vin_n, vspply_p, vspply_n); input vref, vspply_p, vspply_n; inout vout, vin_p, vin_n; electrical vout, vref, vin_p, vin_n, vspply_p, vspply_n; parameter real gain = 3.0 ; parameter real freq_unitygain = 3.0e3; parameter real rin = 1e15 ; parameter real vin_offset = 0.0; parameter real ibias = 10e-6; parameter real iin_max = 10e-6; parameter real slew_rate = 2e6; parameter real rout = 1e12 ; parameter real vsoft = 0.0; real c1; real gm_nom; real r1; real vmax_in; real vin_val; electrical cout;

IC Design Research Laboratory VerilogA (Op Amp) analog ( initial_step or initial_step("dc") ) begin c1 = (1/(3*gain)) * ibias/(slew_rate); gm_nom = 2 * `PI * freq_unitygain * (3 * gain * c1) ; r1 = gain / gm_nom; vmax_in = iin_max/gm_nom; end vin_val = V(vin_p,vin_n) + vin_offset; // // Input stage. // I(vin_p, vin_n) <+ (V(vin_p, vin_n) + vin_offset)/ rin; I(vref, vin_p) <+ 0.0 ; I(vref, vin_n) <+ 0.0 ;

IC Design Research Laboratory VerilogA (Op Amp) // // GM stage with slewing // if (vin_val > vmax_in) I(vref, cout) <+ iin_max; else if (vin_val < -vmax_in) I(vref, cout) <+ -iin_max; else I(vref, cout) <+ gm_nom*vin_val ; // // Parasitic pole // I(cout, vref) <+ ddt(c1*V(cout, vref)); I(cout, vref) <+ V(cout, vref)/r1;

IC Design Research Laboratory VerilogA (Op Amp) // // Output Stage. // I(vref, vout) <+ V(cout, vref) / r1 ; I(vout, vref) <+ V(vout, vref) / rout; // // Soft Output Limiting. // if (V(vout) > (V(vspply_p) - vsoft)) I(cout, vref) <+ gm_nom*(V(vout, vspply_p)+vsoft); else if (V(vout) < (V(vspply_n) + vsoft)) I(cout, vref) <+ gm_nom*(V(vout, vspply_n)-vsoft); end endmodule

IC Design Research Laboratory VerilogA (Delay Generator) module delay_gen(start, Dx, dig_reset,ana_reset, capsel1, capsel0, cap_gnd VB_TC, VBN_DISC, AVDD, AVSS, SVSS); inout start, Dx, dig_reset, ana_reset, capsel1, capsel0, cap_gnd, VB_TAC, VBN_DISC, AVDD, AVSS, SVSS ; electrical start, Dx, dig_reset, ana_reset, capsel1, capsel0, cap_gnd, VB_TAC, VBN_DISC, AVDD, AVSS, SVSS ; parameter real Vth = 2.5 from (1 : 4) ; parameter real logic_low = 0 ; parameter real logic_high = 5 ; parameter real vscale = 1 ; parameter real gmi = 10e-6 ; parameter real tr = 1n ; parameter real tf = 1n ; parameter real vos = 1 from (0.5 : 2.5) ;

IC Design Research Laboratory VerilogA (Delay Generator) real ramp_voltage, tscale, run_status, offset ; analog begin ramp_voltage = 0 ; run_status = logic_low; end begin offset = $realtime ; run_status = logic_high ; end ; if (V(vb_tvc) > 0.5) tscale = 500n ; else tscale = 2u ;

IC Design Research Laboratory VerilogA (Delay Generator) if (V(dig_reset)>Vth) run_status = logic_low ; if (V(stop)>Vth) run_status = logic_low ; if (V(ana_reset) > Vth) ramp_voltage = 0 ; else if (run_status > Vth) ramp_voltage = vscale * ($realtime - offset) / tscale ; if (ramp_voltage > 4) ramp_voltage = 4 ; I(vb_tvc) <+ gmi * V(vb_tvc) ; V(tvc_out) <+ transition(ramp_voltage, 0, tr, tf) + vos ; end endmodule