G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 1

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 2 A Disclaimer This is Not About the “Real” Detector Electronics…

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 3 A Reclaimer This is About 1.Measuring Hadronic Jets to Unprecedented Spatial Resolution 2.Focusing the Electronics Design on this Goal, Optimized for a Test Beam Environment 3.Beginning to Tackle Some (But Not All) of the Problems that Will be Encountered with the Real Detector  This is Only A Step Along the Way…

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 4 Overview of Instrumentation Requirements  Ionization in Gas of RPC Induces Signal on Pad(s)  Fast Current Pulse Flows Between Pads & Signal Return  Pulse Size Depends on Gas & HV - Streamer vs. Avalanche  Active Side of PCB has 1 cm x 1 cm Pads  Top side of PCB Will Contain Front End Electronics  We Will Use Avalanche Mode Anatomy of an RPC Front End Board

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 5 To make the Prototype Hadronic Calorimeter Overview of Instrumentation Requirements

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 6 Overview of Instrumentation Requirements  Hadronic Showers Produce “Hits” on Pads on Each Plane  Hits are Recorded when Charge Deposition on a Pad Exceeds a Threshold  Hits are “Timestamped” to Aid in Event Reconstruction The Nature of Events  Digital Calorimetry Separate e + e - → W + W - υυ and Z 0 Z 0 υυ 30%/√E jet

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 7 GEMs & RPCs  Overall Performance of GEMs is Similar to RPCs Except:  ~X10 Lower Gain  Different Physical Process  Planning to Use Common Basic Architecture  Differences Accommodated in Front End ASIC Overview of Instrumentation Requirements

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 8 Basic System Requirements & Design Choices  Nature of Data: Timestamp & Hit Pattern (Chip ID Appended Later)  Timing Resolution: 100 nS  Overall Event Rate: 100 Hz Max  Noise Rate: ~0.1 Hz/Pad  Live Time: 100% Max Event Rate)  Nature of DAQ: Data Push, High Level of Multiplexing into DAQ  Event Selection & Filtering: High-Level Triggering, Using Geometry & Timestamps  Triggering:  Self-Trigger (Noise, CR)  External Trigger (Test Beam, CR)  External Trigger Gate (Coincidence with Self-Trigger)  System-Generated Trigger (Calibrations) Overview of Instrumentation Requirements  400,000 Readout Channels  1 Bit Dynamic Range  Cheap Electronics  Need Front-End ASIC

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 9 System Description Development Work  Conceptual Design Completed  Semi-Final Design Document Just Released  Collaboration with  Argonne  Boston University  Univ. of Chicago  Fermilab  Univ. of Iowa  Univ. of Texas - Arlington  Development Work In Progress Now

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 10 System Description System Block Diagram  Front End – Includes Custom Front-End Chip & Readout Pads  Back End – Includes DAQ & High-Level Trigger  Trigger System  Timing System

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 11 System Description Front-End ASIC – “DCAL”  Resides On Chamber  Performs Functions:  Receive, Process, & Discriminate Detector Signals  Timestamp Hits, & Record Hit Pattern  Temporary Data Storage  Serial Data Transmission  Gain Switch for RPC/GEM Operation

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 12 System Description Front-End ASIC (Cont.)  Front End Amplifier & Discriminator Senses Hits Above Threshold  24-Bit Timestamp Counter Runs at 10 MHz  Comparator States Clocked into Shift Register - Buffer for Trigger Decision, 20 Stages (2 usec)  Save States & Timestamp on Ext. Trig. or Self-Trigger  Counters Reset Once per Sec, Synchronously Across System  Serial Data Output - 10 Mbit/sec, 88 Bits/Event, ~10 uSec/Event  Serial I/O – Separate Data, Control, & Trigger  Services 64 CH

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 13 System Description Front-End ASIC (Cont.)  Conceptual Design Began in 2003  Collaboration with FNAL ASIC Design Group  Design Work Being Done by Abder Mekkaoui & Jim Hoff

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 14 System Description Front-End ASIC (Cont.)  First Version of Chip Has Been Designed and Fabricated Picture of DCAL ASIC 0.25 micron TSMC Process Photo Courtesy of Ray Yarema

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 15 System Description Front-End ASIC (Cont.)  1 st Prototype in Hand!!  Testing is in Progress  Chip is Functional at Zeroth Level  Performance Testing to Begin Shortly at Argonne

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 16 System Description Front-End Motherboard  Host for DCAL Chips  Contains Pads for Chambers

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 17 Basic Cell Grouping: 8x8 Cells  Front End PC Board - Pads for Chamber System Description Front-End Motherboard (Cont.)

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 18 System Description  Design Multi-Layer Printed Circuit Board  Incorporate Cell Structure and Signal Layers in Composite Multi- Layer PCB ASIC on Opposite Side of Pads Pads on Bottom, ASIC on Top  ASICs on Chamber  Host for DCAL ASIC Front-End Motherboard (Cont.)

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 19  Short Detector Signal Transmission Path, Low Input Capacitance, Close to What is Needed in Final Design, No Dead Spaces from Circuitry, Low Assembly Labor  Digital Noise, Board Complexity  A Challenging Design...  One PCB Contains 24 ASICs, Each Servicing an 8x8 Array of Pads  Arrange Data Connectors on Outside Edge of Chamber System Description Front-End Motherboard (Cont.) 32 cm 96 cm

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 20  To Make A Plane 2 Front End Boards/Chamber 6 Front End Boards/Plane 24 ASICs/FE Board 144 ASICs/Plane 9216 Channels/Plane System Description Front-End Motherboard (Cont.)

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 21  R&D in Progress at ANL to Study Grounding, Shielding, & Noise System Description Front-End Motherboard (Cont.) Readout pads Ground planes LVDS lines LVDS Drivers, Analog Readout of Pads

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 22 System Description Data Concentrator  Concatenate Serial Data Streams from Several Chips  Multiplexer  12 Serial Lines In, 1 Serial Line Out  Drives Serial Line to Next Level of Multiplexing: Super Concentrator  Handles Clock & Control Interface  Handles Trigger Interface

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 23  Data Processing:  Acts as Funnel for Data  Acts as Buffer for Chip to/from Outside World  Adds Chip ID to Data  Has Buffering for Multiple Events  Serial Inputs, LVDS, 10 Mbit/sec  Serial Output, LVDS 10 Mbit/Sec  Needed to Reduce Back-End Costs  Relies on Low Trigger Rate  Implementation with FPGAs System Description Data Concentrator (Cont.)  First Pass at FPGA Design Has Been Completed...

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 24 System Description  Must Also Handle:  Control »Handful of Control Functions Needed for Chips  Timing »Clock - Critical, 10 MHz Dist »Counter Reset - Critical, Sync to 1 Clock Cycle Over Detector  Triggering »Distribution of External Trigger »Use Trigger Gate for Test Beam  LVDS from ASICs  Challenge to Reduce Lines to Minimum  Challenge to Keep Noise Low Data Concentrator (Cont.)

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 25  Host for Data Concentrator Circuitry  Plugs Into Front End Board  Interface for Power Distribution  Forms Integral Unit with Front End PC Board  Plan: Each Data Concentrator Reads Out 12 Chips, or 768 Channels  Connection to Front-End Board System Description Data Concentrator (Cont.)

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 26  Configuration of a Plane 6 Front End Boards/Plane 24 ASICs/FE Board 2 Data Concentrators/FEB 12 Data Conc./Plane System Description Data Concentrator (Cont.)

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 27 System Description Super Concentrator  Concatenate Serial Data Streams from 6 Data Concentrators  Multiplexer  Add Data Concentrator ID  Has Buffering  Drives Serial Line to Back End DAQ  Distributes Clock & Control  Handles Trigger Interface  Similar in Design to Data Concentrator  Fiber Out to Reduce Ground Loops

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 28  Configuration of a Plane System Description Super Concentrator (Cont.)

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 29 System Description Data Collector  Receives Serial Data Streams from Several Super Concentrators  Stores Data in Buffers  Dual Buffers: Data Written into One While Processor Reads the Other  ”Buffer Swaps”  No Deadtime

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 30 System Description  Implementation: 9U x 400mm VME, 12 Inputs  Receives Data Streams  Buffers Read from VME  Also Provides Control on Separate Path  Extensive Use of FPGAs - Provides High Degree of Flexibility Data Collector (Cont.)

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 31  With Super Concentrators, Need 1 Crate, 7 Cards 2 Super Concentrators per Plane 12 Super Concentrators per Data Collector 6 Planes per Data Collector System Description VME, Single-Board Computer, & DAQ (Cont.)

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 32 System Description  Distribute Timing Signals to Front Ends for Timestamping  Provide Timing for Data Collectors & VME Processors  Interface to Beamline System Timing System

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 33  Block Diagram:  Distribute 10 MHz Clock to Front End Chips for Timestamping (100 nS)  Distribute Counter Reset to Front End Chips for Synchronization  Generate Buffer Swaps & 1 Sec. Time Frame Signal for Data Collectors & VME Processors  Interface to Beamline System Timing System (Cont.) System Description  For TB Running, Single Slow Triggers May Not Need Timestamping…

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 34 Summary of System Components Counts of Components  368,640 Readout Channels

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 35 Tasks & Collaborators  Front End ASIC  Front End PC Board  Data Concentrator  Super Concentrator  Data Collector  DAQ, Inc. VME Processor & Software  Trigger Processor, Inc. Hdw. & Soft.  Timing System  Trigger System  Infrastructure, Inc. Crates, Power Supplies, Cabling List of Primary Design Subprojects  FNAL ASIC Design Group  ANL (FNAL)  ANL  (Univ of Chicago)  Boston University  Washington  UTA  (ANL)  See José Repond’s Talk for Organization, Funding, & Politics

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 36 Near-Term Plans  Complete Bench Testing of Chip  Design Interface to Prototype Chambers – Cosmic Ray Hodoscope & Test Beam Chip Testing & Characterization

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 37 Near-Term Plans  Decrease Gain of Front-End Amplifier  Synchronize Serial Clock to Timestamp Clock  Implement Complete Triggering Features  Change Bonding Pads for Standard Packaging  Other?... Complete Next Iteration of Chip  May Need (Probably Need) 2 nd Prototype Submission…

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 38 Near-Term Plans Consider Use of CRC for Data Collector  Replaces Data Collector and Super Concentrator  Each Input Services 1 Plane (Formerly 2 Super Concentrators)  Only Needs FPGA Code?...  LVDS Copper, Not Fiber…  Could Save Cost, and Streamline System Integration with ECAL  We Will Pursue with Paul & RAL Photo Courtesy of Paul Dauncey

G. Drake Electronics for DHCAL R&D Oct. 13, 2005 p. 39 Summary Significant Progress has been Achieved with System Design First Version of Custom ASIC in Hand Preliminary Design Work in Progress on Front-End Board & Data Concentrator Will Work on Optimizing Back End Implementation  Chip is Functional, Testing in Progress, Iteration Needed