MMIC Design in 0.13µm SiGe BiCMOS Process by Hans Schou and Magnus Pallesen

IHP SG13S 0.13 µm SiGe HBT BiCMOS 1.2 V HBT with fT=250 GHz 3.3 V HBT with fT=50 GHz 1.2 V logic CMOS 3.3 V I/O CMOS

NPN Layout Configurations

SG13S Stackup

Design of a 60 GHz Low Noise Amplifier in a 0.13 µm SiGe BiCMOS Process By Magnus Pallesen

LNA Specifications

Design Methodology Determine number of stages, topology and bias. Design as single stages with ideal components. Cascade single stages to multistage amplifier. Replace inductors with T-lines.

Topology Preferably both Common Emitter and Cascode Matching problems with Cascode due to high output impedance. CE best alternative.

Bias Trade-off between power consumption, gain and noise

Multistage design VBB=850 mV Optimized for Low noise VBB=850 mV Medium gain Medium nosie VBB=880 mV Optimized for high gain CE Trade-off between power consumption, noise, bandwidth and gain

Simulated Performance

Post Layout Schematic

Layout 320µm 411µm

Simulated Performance

Design of a 60 GHz Power Amplifier in 0.13 µm SiGe BiCMOS By Hans Schou

Power Amplifier Design Goals

Class AB operation at VBB=0.85

Output Stage Port Parameters High reverse transmission, S12

Three Stage Amplifier Three common emitters Tuned for maximum output power

Simulated Performance

Schematic

Simulated Performance

Questions?