Organization for Micro-Electronics desiGn and Applications HGCAL Front-End Electronics Christophe de LA TAILLE, Marcello MANNELLI sept 2015

Detector overview HGCAL electronics 2 Si sensor FE-ASICs Module Cassette Stringent requirements for Front-End Electronics –Low power (few mW), low noise (<2000 e-) –High radiation (200 Mrad, 10 E 16 N) –System on chip (digitization, processing…) –High speed readout (5-10 Gb/s)

3 Front-End electronics Baseline : charge + ToT [J. Kaplon] –Charge readout fC (0-80 MIP) 10 bits –Time over Threshold ( pC) ( MIPs) : 12 bits –In addition : timing information to 50 ps accuracy Variants : more classical readout (bi-gain) or switched feedback [Omega] HGCAL electronics

Electronics issues Several key issues to be studied : –Noise –Resolution –Stability –Linearity –Accuracy –Calibration –crosstalk –Radiation –Timing –Systematic effects And also –65/130 nm –System issues –Trigger path HGCAL electronics 4 1 pC 200 MIPS

Electronics for testbeam [J. Incandela et al.] Testbeam electronics –Use SKIROC2 to exercise system issues (low noise, large range) –Complex front-end boards designed at UCSB : delicate routing [M. Miller] –Evolutive readout designed at FNAL –First tests before end 2015 HGCAL electronics 5

Readout [P. Rubinov et al.] Evolutive DAQ –FMC cards in 6U crates (FPGA Mezzanine Card) –Daughterboards supporting 2 wafers –Ethernet readout –Zynq7000 based –Also provides power to wafers –Kapton flat cable and low profile connectors chosen Ready to manufacture HGCAL electronics 6

HGCAL tests for electronics Development of a SKIROC2A for CMS –Optimized version for CMS testbeam, pin to pin compatible –Dual polarity charge preamplifier –Faster shapers (25 ns instead of 200 ns) –40 MHz circular analog memory, depth= 300 ns –TDC (TAC) for ToA and ToT, accuracy : ~50 ps –Submission end 2015 SiGe 350nm Will replace SKIROC2 on modules for timing studies HGCAL electronics 7 SKIROC2

Test vehicles 65/130 nm Test vehicles (Analog chips 130nm / 65 nm) –Variants of Preamplifiers NMOS & PMOS with variable Cf –Possibly variable shaper –Discriminator for ToT –Calibration circuit –Submission end 2015 Readout issues / Digital part –Related to analog VFE –High speed/performance digital circuitry would be best achieved with 65 nm –Impact on power also significant –Global view important for overall optimization HGCAL electronics 8

Tests for high speed PCB link [E. Frahm] HGCAL electronics 9 1 m trace driven at 4.8 Gb/s –2 different high quality PCB types –Diffrential drivers with re-timer DS110DF410 –Passive equalizers MAX3787 Very good performance with passive equalizers or de-emphasis Allows to consider such links, maybe at even higher speed

Plans and schedule Several tests will be performed on electronics next year –Test vehicles in 65 and 130 nm with TOT architecture and backup options (bi-gain or gain-switching) –Tests with SKIROC2 (noise, resolution, tests with sensors..) –System tests with modules –Tests with SKIROC2CMS (timing accuracy, resolution…) complementary to test vehicles and system tests Finalizing the FE chip architecture will rely on their results –It would be reasonable to wait for them before freezing the design –In parallel progress can be made on digitization, digital part readout and trigger paths –Interaction also with low power GBT group for HGC requirements HGCAL electronics 10

Backup HGCAL electronics 11

Gain switching characteristic 12

Global architecture of the ASIC  2 or 4 ASICs per sensor (128 or 256 channel sensor)  Digital sum should be more power efficient: 1 ADC stage less compared to analog alternative  But, digital sum “ADC / TDC” need to be studied (ADC bin different of TDC bin)  VFE choice will impact digital part  ASIC size should be dominated by L1 latency memory (64 times)  would prefer 65 nm  ASIC is 64 channels  2 serial links (data L1 + trigger) HGCAL electronics 13