UPDATE ON HARDWARE 1 1.VERTICAL SLICE & COOLING TESTS 1.ONLY a TEST STAND or a SMALL DEMONSTRATOR ?? 2.CRATE

Autumn 2011: Vertical Slice Option 1- baseline (for a run stop in 2012) Good as test stand for new prototypes, Good to connect to ROSs, Good to send data to calibration stream 2 Marco - FTK review Pixel clust. S-links Pixels Fired channels Roads S-link Filar board as interface between SLINK and PC NEXT: WE WILL USE a TILAR

3 Marco - FTK review Pixel clust. S-links Pixels Fired channels Roads + hits S-link Filar board as interface between SLINK and PC DO S-link Tracks GigaFitter Vertical Slice Option 1I: a Small Demonstrator ADD the Data Organizer & GigaFitter

THE VERTICAL SLICE PLAN for Option II (to be done only if the run is exended to 2013) 4 Bank size, data flux evaluation Hardware size Hardware task list Software task list (related to hardware) Software task list (related to ROSs) Software task list (related to HLTs)

5 PATTERN size r-  : 48 pixel, 40 SCT, 72 pix z - 3 pixels + 3 inner SCTs (2.4 mm)(3.2 mm)(28 mm) GUIDO IS STUDYING a 6-Layer bank to be used PATTERN size r-  : 48 pixel, 40 SCT, 36 pix z - 3 pixels + 3 inner SCTs (2.4 mm)(3.2 mm)(14 mm) PATTERN size: 48 pixel, 40 SCT, 72 pix z - 3 pixels + 2 inner + outer SCTs (2.4 mm)(3.2 mm)(28 mm) PATTERN size: 48 pixel, 40 SCT, 36 pix z - 3 pixels + 2 inner + outer SCTs (2.4 mm)(3.2 mm)(14 mm) 6 Layers Inner SCTs 48x40x36 full barrel 1 AMBs with CDF chips: 0,64 MP → 1 wedge 2 MP ~ 3 AMBoards coverage ~ 90%

6 EDRO #2 EDRO #3 EDRO #0 3 EDROs + 3 AMBs (anyhow we need to build 6 of them for cooling tests), EDROs with 2 mezzanine each, Some links are used for overlaps Slinks ~  x  ~ 1 x ,9 MP 3.How many hits per event? 4.How many roads per event? (Guido work) 5.How many fits per event?

7 The average number of hits (TP) per logical silicon layer per core crate for WH events at 75 pile-up events Linear with 23 pile-up events, ½ Barrel-1 region: ~ 190 average number of clusters / layer /event. Taking into account the overlap or better coverage as a function of Zvertex: could double for pixels number. TO BE COMPARED TO A ALLOWED MAXIMUM of 533 We work at 40 MHz clock = 25 ns clock cycle 75 kHz L1 max rate → 13.3 us minimum average time/event → we can load 13300/25= 533 average # of clusters per layer per event CHECK ON CLUSTER FLUX

8 CHECK ON ROAD FLUX WH 23 pile-up events : PATTERN size r-  : 48 pixel, 40 SCT, 72 pix z 1,0 MP (max 1.9MP - 3 AMBs) in half barrel (coverage ~ 95%) 3500 /board/ ½ Barrel region PATTERN size r-  : 48 pixel, 40 SCT, 36 pix z 1,0 MP - 3 AMBs in half barrel (coverage ~ 90%) 1300 /board/ ½ Barrel region Max kHz input event rate Need a powerful Data Organizer firmware or TRY also thinner-different-shape roads 41(0,25 phi pix module) x24 (0,0625 SCT module)x144 (full in z)

9 CHECK ON FIT FLUX From previous barrel studies: 17.6 (5 MP) ^3 fits/ event/subregion 57 10^3 fits/ ½ Barrel region/event Let’s wait Guido Results with 6 layers thinner roads ! For a max L1 rate: 57 x 10^3 fits x 75 x 10^3 event/sec = 4,2 x10^9 fit/sec Cut down a little bit, to be compatible with GigaFitter capability. But we have to exploit parallelization at the best. New mezzanine for multiple links from EDRO-to- GF? Multiple DOs inside the EDRO? Slink

10 To be done on the FTK side to build the small Demonstrator proposal 1.Generate the banks with 6 layers (3 pixels and 3 inner SCT axial layers or other configuration) GUIDO (necessary for the baseline also – but less critical) 2.Choose the specific detector modules to be used, define the overlaps. DF people needed (at least part of this is necessary for the baseline). Can Fermilab do it? 3.Install enough Holas choosing the right detectors selected in point 2 (Chicago + ?) 4.Fill 12 LAMBs + spares (CDF LAMBs + chips added on the back) (Pisa – needed also for cooling tests) 5.Build 3 AMBoards+spare with the power necessary for 128 Amchips (Pisa - we need to build 6 of them for cooling tests) 6.Build 3 EDROs+spare with all mezzanines (Bologna) 7.Recover the GFs from CDF and adapt firmware (Pisa) 8.Hola provided of SVT connectors for EDRO output easily connected to GF 9.Test these boards and commission them. (each one his boards) 10.Connect the GF output to the Ros (Andrea & Jinlong) 11.Write the software to initialize/ control the crate (needed for the baseline olso, but simplified) 12.Write the software for the spy buffer diagnostic system (needed for the baseline olso, but simplified) 13.HLT for muon identification & track-based isolation, + primary vertex identification (Giagu and Genova people) 14.Phisics case (everybody)

Plan: John Bain proposal Milestones: 1.integration into the DAQ: running in a separate partition which would exercise the whole DAQ chain, writing to a separate stream from the physics data. 2.demonstrate that we can be run and read out at the full rate without dead-time and that, in the case of problems, corrective action (e.g. stopless recovery) can be taken with minimum interruption to data-taking. Initially we would need to exercise the system outside of physics running in cosmic running and high-rate tests. 3.to record collisions data containing the FTK results in the event. Re-run the HLT in offline reprocessing and compare online results with what we would get from FTK. Events written to calibration stream with the whole detector data plus FTK tracks 4.testing the use of FTK information in the HLT. E.G. beam position measurements for cosmic chains or in the tail of fills.

12 1)Integration in a test-bed in the lab 2) Tests at P1 in a separate partition with fake input 3) Running in a separate partition with data from ATLAS during cosmic running 4) Running in a separate partition with data from ATLAS during physics running 5) Running in the ATLAS partition during cosmic running with FTK data sent to the EB and read out into a calibration stream. a) with no data requests from L2 to FTK b) defining a cosmic chain that requests and uses FTK info. 6) Running in the ATLAS partition during physics running with FTK data sent to the EB and read out into a calibration data-stream. (no data requests from L2 to FTK). 7) Define 1 or more non-triggering chains at the HLT that uses FTK data. This could be a muon isolation chain, b-jet chain or b-physics chain run in monitoring mode. But perhaps the best test would be a beamspot chain Summary John Bain proposal (if ATLAs takes data in 2013 we will add points)

13 CRATE & RACK TESTS CRATE Wiener new quotation Other quotations & proposals? Peak Output: 5V/345A, 3,3V/115A, 48V /81A, UEV 6021 Bin, 12U high, 64xP-VIPA backplane Euro Fan tray EX item No. 0F00.060B 9-fold, 680mm bottom inlet 1 off Euro Modular VHF switching power supply UEP 6021, Euro 19’’ Rack assembly / Power bin 6U 769 Euro TOT 15 Keuros PLAN to BUY 2 of them this year for a RACK TEST in 2012

14 CONCLUSIONs We have 2 possible scenarios: 1.run stops in 2012: baseline Vertical Slice + FTK demonstrator initial 2015 run 2.run stops in 2013: advanced Vertical Slice for an early demonstrator, exploiting CDF hardware and multiple EDROs (almost same hardware needed for cooling tests) We need to assign tasks, in particular the ones related to the baseline Vertical Slice to be integrated at CERN next autumn - proposal: 1.Generate banks with 6 layers GUIDO 2.Choose specific detector modules to be used Fermilab + Annovi? 3.Install enough Holas choosing the right detectors (as point 2) (Chicago + ?) 4.Fill 12 LAMBs (CDF LAMBs + chips added on the back) (Pisa for cooling tests) 5.Build 3 AMBoards+spare with 48V for128 AMs (Pisa - 6 needed for cooling tests) 6.Build 3 EDROs+spare with all mezzanines (Bologna) 7.FTK tracks used in MUON identification and Isolation (Giagu)