1 The Registers File l Modern digital systems are based on logic with state variables, which are changed according to a clock. – The system consists of two types of logic -- combinational and sequential. – Sequential logic contains state elements or memory elements. State element 1 State element 2 Combinational Logic The simplest type of clocking system to understand is built with edge triggered state elements. The diagram shows a system which clocks on the leading edge of the clock. leading edge leading edge clock period

2 Flip-Flop l An S-R flip-flop: R=1 S=0 Q=0 Q=1 R=0 S=1 Q=1 Q=0 R=0 S=0 Q=0 Q=1 R=0 S=0 Q=1 Q=0

3 Simple State Element S-R Latch (Or S-R Flip-Flop) – Feedback is the key to memory/state elements. – Once a value is fed to the element, it circulates inside the element and renews itself, even after the input is turned off. – Other memory devices can be built from the basic latch. R SR S Q Q QQRS Save Illegal

4 NAND Based S-R Flip-Flop QQRS Save 11 RSRS Q=0 Q=1 Illegal

5 Clocked "D" Latch l This latch has one input, called "D". l When the clock is low, AND gates force zero on all inputs to the S-R latch  no change in state. l When clock is high, the value at D sets the "S" input of the latch; inverted D sets the "R" input of the latch. Clock D Q Q

6 "D" Latch Clocking Waveforms The output "D" responds to the change in input, a characteristic delay after the clock goes high. Clock D Q Q DCQDCQ t delay t t

7 J-K Flip-Flop l The undefined state of the SR type is defined in the JK type. l Inputs J and K behave like inputs S and R to set and clear the flip-flop – note that in a JK flip-flop, the letter J is for set and the letter K is for clear). l When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state, i.e. if Q=1, it switches to Q=0 and vice versa.

8 J-K Truth Table

9 T Flip-Flop l the T flip-flop is obtained from the JK type if both inputs are tied together. l If T=1, the output of the T flip-flop will "toggle" with each clock pulse. l If T=0, the output of the T flip-flop will not be changed

10 Q(t)Q(t+1)JK 000  011  10  1 11  0 JKFF Q(t)Q(t+1)SR 000   0 SRFF Q(t)Q(t+1)D DFF Q(t)Q(t+1)T TFF Excitation tables

11 Edge Triggered "D" flip-flop D Clock Q Q D Latch D C Q D Latch D C Q The first latch is called the master, the second latch is called the slave. l When the clock goes high, the first D latch (master) accepts the change in input l Because of the inverter, the change is blocked from moving on the second D latch (slave). l When the clock goes low, the slave latch accepts the change in input.

12 Edge Triggered Timing D Clock Q Q D Latch D C Q D Latch D C Q D Clock Master Clock Slave Q

13 Registers Registers can be built from a series of Edge Triggered (ET) D latches connected to the same clock. Clock ET-D Latch D C Q ET-D Latch D C Q ET-D Latch D C Q... ET-D Latch D C Q D0D1D2D(n-1) Q0Q1Q2Q(n-1)

14 Registers File Implementation of double read port read reg 1 read reg 2 write reg write data write enable read data 1 read data 2 register 0 register 1... register 30 register 31 MUXMUX MUXMUX data 1 data 2 read reg 1 read reg 2 5 bits 32 bits 5 bits 32 bits 1 bit

15 Write Port Implementation n-to-1 decoder register 0 register register 30 register 31 CDCD CDCD CDCD CDCD CDCD write enable write data Reg # 32 bits 1 bit 5 bits Clock 1 bit