VLSI 1 382M/460R Lab 2 DESIGN OF AN ARITHMETIC LOGIC UNIT (ALU)

Lab 2 Goals Become Familiar with Gate Level Design Flow Learn More Tools Design and Optimize for Speed Choose a good structure Perform logic reduction Compete in Speed

Arithmetic Logic Unit (alu) alu a[15:0]b[15:0] code[4:0] cin ab cout vout c[15:0] 16 5

Arithmetic Logic Unit (alu) a[15:0]b[15:0] code[4:0] cin cout vout c[15:0] 16 5 LogicCompareShifterAdder MUX

Logic Arithmetic A OR B A XOR B NOT A A AND B Logic a[15:0]b[15:0] code[4:0] c[15:0]

Condition Operation Less than Less than or equal Greater than Greater than or equal Equal Not equal Compare a[15:0]b[15:0] code[4:0] c[15:0]

Shifter Logic Left Logic Right Arithmetic Left Arithmetic Right Rotate Left Rotate Right Shifter a[15:0]b[15:0] code[4:0] c[15:0]

Shifter Logic shifts should shift in 0's Arithmetic left shift should shift in 0's Arithmetic right shift should shift in the most significant bit Rotate left shift should shift out the most significant bit to the least significant bit Rotate right shift should shift out the least significant bit to the most significant bit

16-bit Adder a[15:0]b[15:0] code[4:0] cin cout vout c[15:0] bit adder

16-bit Adder Options Signed addition Unsigned addition Signed subtraction Unsigned subtraction Signed increment Signed decrement

16-bit Addition a[15:0] b[15:0] cin cout vout c[15:0] Overflow

Overflow (vout) Indicates Your Result Is Wrong The result exceeds the data width Situations That Can Cause Overflow P + P = N N + N = P P – N = N N – P = P

Design Flow in Lab 2 Design Derive schematic Verify Functionality Timing Analysis Place & Route Timing Analysis Compete in Speed at this Point

Design Text - Chapter 11, Section 2 Class notes External experience/research Innovation Family secret

Schematic Design Given standard cells complete with timing information INVX1, INVX4, NAND2X1, NOR3X1 No other components allowed (unless designed with standard cells) No memory elements Number indicates drive strength

Verify Functionality Tool: Verilog-XL Verify the gate level verilog netlist you design Write testfixture.verilog with test cases given on the web

Timing Analysis Tool: Primetime Text-based static timing analysis (STA) Reads in gate level verilog netlist Outputs critical path and delay

Primetime STA

Place & Route Tool: Encounter Layout completed by auto place and route (APR) Run timing analysis pre and post-layout (alu only)

Layout

Grading Lab A Part A takes 50% of total score in Lab 2 Functional Correctness: 30% Performance: 15% (Your max delay) Lab Report: 5% (Your explanation of your design) Lab B Part B takes 50% of total score in Lab 2 Functionality Correctness: 25% Speed: 15% APR correctness: 5% Lab Report: 5%