UNIT 2

CPUXV2 20-bit addressing User-definable Boot Strap Loader RAM starts at 0x1C00 Beginning of MAIN flash moves according to RAM Vector table starts at 0xFF80

Switch ̲ State Input ̲ Pin ̲ State Open(Not Pressed) Undefined Closed (Pressed) High (Equal to VCC) Switch ̲ State Input ̲ Pin ̲ State Open(Not Pressed) Undefined Closed (Pressed) Low (Equal to GND)

Switch ̲ State Input ̲ Pin ̲ State Open(Not Pressed) Low Closed (Pressed) High (Equal to VCC) Switch ̲ State Input ̲ Pin ̲ State Open(Not Pressed) High Closed (Pressed) Low (Equal to GND)

GPIO -The MSP430 uses a limited number of GPIO hardware pins -The pins are organized into ports, with each port usually one byte (8 bits/pins) wide. -You can set each pin's function independently (input or output) by modifying some memory mapped I/O registers. There are several registers associated with each port. For now, you only need to worry about four (P1IN, P1OUT, P1DIR, and P1REN)-example for Port1. P1IN Reading P1IN reads the entire port, regardless of pin direction. P1OUT To set P1OUT, use a mov.b instruction to set several pins at once. To set individual bits to "1",you can use an or.b instruction with a "1" in the positions you want to set. P1DIR Set the corresponding bits to "0" to set pins to input mode, or to "1" to set them to output mode. P1REN Set the corresponding bits to "1" to enable a pin's pullup resistor, or to "0" to disable it (disabled by default).

Interrupts preempt normal code execution Interrupt code runs in the foreground Normal (e.g. main() ) code runs in the background Interrupts can be enabled and disabled Globally Individually on a per-peripheral basis Non-Maskable Interrupt (NMI) The occurrence of each interrupt is unpredictable When an interrupt occurs Where an interrupt occurs Interrupts are associated with a variety of on-chip and off-chip peripherals. Timers, Watchdog, D/A, Accelerometer etc.. Interrupts are commonly used for urgent tasks which are highest priority than main code

Interrupt Flags Each interrupt has a flag that is raised (set) when the interrupt occurs. Each interrupt flag has a corresponding enable bit– setting this bit allows a hardware module to request an interrupt. Most interrupts are maskable, which means they can only interrupt if 1) enabled and 2) the general interrupt enable (GIE) bit is set in the status register (SR).

The CPU must know where to fetch the next instruction following an interrupt. The address of an ISR is defined in an interrupt vector. The MSP430 uses vectored interrupts here each ISR has its own vector stored in a vector table located at the end of program memory Interrupt Vector

Interrupt Service Routines Look superficially like a subroutine. However, unlike subroutines  ISR’s can execute at unpredictable times.  Must return using reti rather than ret. ISR must handle interrupt in such a way that the interrupted code can be resumed without error Interrupt-related runtime problems can be exceptionally hard to debug Returning from ISR MSP430 requires 6 clock cycles before the ISR begins executing The time between the interrupt request and the start of the ISR is called latency (plus time to complete the current instruction, 6 cycles, the worst case) An ISR always finishes with the return from interrupt instruction (reti) requiring 5 cycles

MASKING OF INDIVIDUAL BITS A pattern used for selecting bits is called a mask and has all zeroes except for a 1 in the position that we want to select. if ((P1IN & BIT3) == 0) { // Test P1.3 // Actions for P1.3 == 0 } else { // Actions for P1.3 != 0 } Setting a bit is done using Inclusive OR operation- x|0 =x and x|1 =1 we could set (force to 1) bit 3 of port 1 with P1OUT = P1OUT | BIT3, P1OUT| = BIT3; Clearing a bit (to 0) is done using AND operation- x & 0 = 0 and x & 1 = x. P1OUT &= ˜ BIT3 Bits can be toggled (changed from 0 to 1 or 1 to 0) using the exclusive-or operation. For example, P1OUT ˆ= BIT3 toggles P1OUT.3.

#include void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer P1DIR |= 0x01; // Set P1.0 to output direction P1IE |= 0x10; // P1.4 interrupt enabled P1IES |= 0x10; // P1.4 Hi/lo edge P1IFG &= ~0x10; // P1.4 IFG cleared _BIS_SR(LPM4_bits + GIE); // Enter LPM4 w/interrupt } // Port 1 interrupt service routine #pragma vector=PORT1_VECTOR __interrupt void Port_1(void) { P1OUT ^= 0x01; // P1.0 = toggle P1IFG &= ~0x10; // P1.4 IFG cleared }

#include void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR |= 0x01; // P1.0 output TACTL = TASSEL_2 + MC_2 + TAIE; // SMCLK, contmode, interrupt _BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt } // Timer_A3 Interrupt Vector (TAIV) handler #pragma vector=TIMERA1_VECTOR __interrupt void Timer_A(void) { switch( TAIV ) { case 2: break; // CCR1 not used case 4: break; // CCR2 not used case 10: P1OUT ^= 0x01; // overflow break; }

Supervision mode Ensure correct working of software program Perform PUC Generate interrupt when counter overflows Interval timer Independent timer generates standard interrupt when counter overflows periodically WDTCNT is not directly accessible to the user WDT controlled by WDTCTL register

#include // Specific device // Pins for LEDs and button #define LED1 P2OUT_bit.P2OUT_3 #define LED2 P2OUT_bit.P2OUT_4 #define B1 P2IN_bit.P2IN_1 // Watchdog config: active, ACLK / > 1s interval; clear counter #define WDTCONFIG (WDTCNTCL|WDTSSEL) // Include settings for _RST/NMI pin here as well void main (void) { WDTCTL = WDTPW | WDTCONFIG; // Configure and clear watchdog P2DIR = BIT3 | BIT4; // Set pins with LEDs to output P2OUT = BIT3 | BIT4; // LEDs off (active low) for (;;) { // Loop forever LED2 = ˜IFG1_bit.WDTIFG; // LED2 shows state of WDTIFG if (B1 == 1) { // Button up LED1 = 1; // LED1 off } else { // Button down WDTCTL = WDTPW | WDTCONFIG; // Feed/pet/kick/clear watchdog LED1 = 0; // LED1 on } WatchDog Timer EXAMPLE

What Clocks Do You Need?  Fast Clocks CPU, Communications, Burst Processing  Low-power RTC, Remote, Battery, Energy Harvesting  Accurate Stable over ⁰/V, Communications, RTC, Sensors  Failsafe Robust–keeps system running in case of failure  Cheap … … or some combination of these features? MSP430's rich clock ecosystem provides three internal clocks from a variety of clock sources. Heart beat of our system Operating modes ---- BOR  POR  PUC  Active (AM)

VLO : Very Low-frequency Oscillator (VLO) extremely low-power Ex: reading a sensor REFO: REFerance Oscillator (REFO) common "watch crystal" frequency Ex:RTC XT1 and XT2 eXTernal clock inputs Not all devices provide both Ex:RTC,USB DCO: Digitally Controlled Oscillator (DCO) fast start-up time Ex:CPU & many high-speed peripherals MODOSC: MODuale OSCillator (MODOSC) Didicated to ADC

Main features of the MSP430 families: Low power consumption (around 1 mW/MIPS or less) Battery operated embedded systems devices. This goal can only be accomplished using a design utilizing low power operating modes. The total power consumption depends on several factors: Clock frequency ambient temperature supply voltage Peripheral selection input/output usage memory type.

Low power modes

Principles For ULP Applications MSP430 is inherently low-power, but your design has a big impact on power efficiency  Use interrupts to control program flow  Maximize the time in LPM3  Replace software with peripherals  Configure unused pins properly  Power manage external devices  Efficient code makes a difference Every unnecessary instruction executed is a portion of the battery that’s wasted and gone forever

 Ferroelectric RAM (FRAM) is similar to Dynamic RAM (DRAM) – except that FRAM uses ferroelectric capacitors – as opposed to traditional (dielectric) capacitors  The ferroelectric crystal contains a dipole whose atom can be moved into an up or down state based upon the application of a field.  The atoms position can then be sensed, allowing us to read its value.  The processes of setting the dipole’s state can be done with as little as 1.5 Volts-no charge pump required