ASIC-LOP/LSTP Roadmap Assumptions - Vdd: equals to the HP proposal of USA. But trend is different with each other. - Performance: 10%/year growth.

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Presentation transcript:

ASIC-LOP/LSTP Roadmap Assumptions - Vdd: equals to the HP proposal of USA. But trend is different with each other. - Performance: 10%/year growth for LOP 5%/year growth for LSTP - Max. Ig: 100pA/um for LOP (no scaling) 1pA/um for LSTP (no scaling) - Ioff : Equals to the max. Ig of each LOP and LSTP. 16/7/2001 PIDS-Japan - Id-NMOS : for LOP (no scaling) for LSTP (no scaling)

Vdd in MPU(V) Vdd in ASIC/L(O)P (V) Maximum Ig per Tr (pA/1um) ASIC/L(O)P 100 Maximum Ig per Tr (pA/1um) ASIC/L(ST)P Tox,eq in MPU (nm) Tox,eq in ASIC/L(O)P (nm) Tox,eq in ASIC/L(ST)P (nm) Id-NMOS at Vdd (uA/um) ASIC/L(O)P High-k is put off one year, because of SiON and N/O leakage improvement Maximum Ioff at 25C (pA/um) ASIC/L(O)P 100 Maximum Ioff at 25C (pA/um) ASIC/L(ST)P Id-NMOS at Vdd (uA/um) ASIC/L(ST)P 16/7/2001 PIDS-Japan Vdd in ASIC/L(ST)P (V) Performance L(O)P Performance L(ST)P ASIC/LOP, LSTP Roadmap

Gate leakage (A/cm 2 ) Physically effective oxide thickness (nm) 1E-10 1E-8 1E-6 1E-4 1E-2 1E 0 Pr 2 O 3 La 2 O 3 SiO 2 Al 2 O 3 ZrO 2 Ta 2 O 5 HfO 2 Gate leakage current vs. insulator Limit in LOP/ASIC Limit in MPU Limit in LSTP/ASIC 1E 2 ITRS ’ PIDS-Japan SiON TiO 2 N/O (Revised) VLSI ‘01