Research on 3-D Parasitic Extraction and Interconnect Analysis Wenjian Yu EDA Lab, Dept. of Computer Science & Technology, Tsinghua University Beijing, P. R. China

2 Outline Background BEM Solver for Capacitance/ Resistance Extraction Frequency-Dependent Reluctance / Impedance Extraction Substrate Parasitic Extraction Other Works on Interconnect Modeling/ Analysis

3 Background Parasitic extraction in deep-submicron VLSI Interconnect dominates circuit performance Interconnect delay > device delay Crosstalk, signal integrity, power, reliability Other parasitics in SOC Substrate coupling in mixed-signal circuit Interconnect parasitic extraction Resistance, Capacitance and Inductance Becomes a necessary step for performance verification in the iterative design flow Parasitic parameters should be extracted accurately

4 From electro-magnetic analysis to circuit simulation Parasitic extraction / Electromagnetic analysis Thousands of R, L, C Filament with uniform current Panel with uniform charge Model order reduction Reduced circuit

5 Background Research Focus Fast numerical methods for 3-D field solver Considering emerging problems for interconnect modeling and analysis Team & Collaboration 1 Ph.D student, 3 master students 2 undergraduates/spring semester Collaborate with Prof. Hong’s team With Prof. Z. Yu’s team at IME of Tsinghua Univ. With Prof. C-K Cheng’s team at UCSD

6 Outline Background BEM Solver for Capacitance/ Resistance Extraction Frequency-Dependent Reluctance / Impedance Extraction Substrate Parasitic Extraction Other Works on Interconnect Modeling/ Analysis

7 QBEM - QMM accelerated BEM Features of QBEM 3D field solver in the LPE flow Has similar input format to Raphael RC3 Same boundary assumption as Raphael Several tens to hundreds faster than Raphael; 10x faster than FastCap Algorithms inside Based on the multi-zone boundary element analysis. The original dielectrics are cut into fictitious medium regions, to maximize the sparsity of matrix A ( Ax =b is solved). Efficient techniques of storing sparse matrix and Krylov iterative solver are used to exploit the matrix sparsity for performance improvement.

8 QBEM - QMM accelerated BEM A 3-D multi-dielectric case for capacitance extraction

9 QBEM - QMM accelerated BEM Handling of complex structures Bevel conductor line; conformal dielectric Structure with floating dummy fill Multi-plane dielectric in copper technology Metal with trapezoidal cross section 3-D resistance extraction Complex 3-D structure with multiple vias Improved BEM coupled with analytical formula Extract DC resistance network Hundreds/thousands times fast than Raphael, while maximum error <3%

10 Calculate boundary capacitance matrix Combine the BCMs to get the final result. HBBEM: Hierarchical Block BEM Features of HBBEM 3D field solver for capacitance extraction Same BEM kernel as QBEM, but directly get the capacitance matrix, without setting bias voltages for many times Faster than QBEM for matrix extraction Extension & Application Full-chip parallel extraction, combined with an overlap- combination approach Employed by CSurf: IBM’s primary 3-D solver Partition of 3-D Structure 3-D BEM Block

11 Relevant publications W. Yu, Z. Wang, J. Gu, “Fast capacitance extraction of actual 3-D VLSI interconnects using quasi-multiple medium accelerated BEM,” IEEE Trans. Microwave Theory Tech., Jan 2003, 51(1): W. Yu, Z. Wang, “Enhanced QMM-BEM solver for 3-D multiple-dielectric capacitance extraction within finite domain,” IEEE Trans. Microwave Theory Tech., Feb 2004, 52(2): X. Wang, D. Liu, W. Yu, Z. Wang, “Improved boundary element method for fast 3-D interconnect resistance extraction,” IEICE Trans. on Electronics, Feb. 2005, E88-C(2): M. Zhang, W. Yu, Z. Wang, “Efficient 3-D extraction of interconnect capacitance considering floating metal-fills with boundary element method,” IEEE Trans. Computer-Aided Design, Jan 2006, 25(1): T. Lu, Z. Wang, W. Yu, “Hierarchical block boundary-element method (HBBEM): A fast field solver for 3-D capacitance extraction,” IEEE Trans. Microwave Theory Tech., Jan. 2004, 52(1): 10-19

12 Outline Background BEM Solver for Capacitance/ Resistance Extraction Frequency-Dependent Reluctance / Impedance Extraction Substrate Parasitic Extraction Other Works on Interconnect Modeling/ Analysis

13 Background of inductive effect Inductive effects becomes increasingly significant Long metal interconnects Higher clock frequency Reduction in on-chip resistance and capacitance (copper, wider upper-layer metal, low-k dielectric) Frequency-dependent inductance / impedance High-frequency skin effect and proximity effect Model off-chip structures, or on-chip high-lever wide interconnects Different electromagnetic analysis: MQS, EMQS, full-wave Methods: PEEC(volume discretization), BEM, FEM

14 Reluctance is the inverse of partial inductance K was proposed by Devgan et. al (ICCAD’2000): [K] = [L] -1 Has the locality property like capacitance Easily sparsified for acceleration of extraction and simulation Frequency-dependent reluctance extraction General window technique Efficient intra-window extraction Directly extract K without inversion from L Matrix condensation and GMRES solution Reuse of filament inductances At least 50 times faster than FastHenry for off-chip structures, or on-chip P/G nets Reluctance (K) extraction

15 BEM has some advantages over volume discretization Surface discretization, independent of frequency Extends to full-wave analysis MIT proposed FastImp based on BEM Our work A reuse scheme of the boundary integrals in FastImp for multi-frequency extraction shows 2 -3 times speedup Mixed BEM which combines the direct BIE with an indirect BIE for conductor domain Reduce #unknown from 7N to 4N About 2 times faster than FastImp BEM-based impedance extraction Full wave

16 Relevant publications Papers M. Zhang, W. Yu, Y. Du, Z. Wang, “An efficient algorithm for 3-D reluctance extraction considering high frequency effect,” ASP-DAC 2006, Japan, Jan. 2006, pp C. Yan, W. Yu, Z. Wang, “Application of the complete multiple reciprocity method for 3D impedance extraction with multiple frequency points,” Engineering Analysis with Boundary Elements, Aug. 2006, 30(8): W. Yu, C. Yan, Z. Wang, “A mixed surface integral formulation for frequency-dependent inductance calculation of 3D interconnects,” Engineering Analysis with Boundary Elements, 2007, 31(10): F. Gong, W. Yu, et. al, “ Efficient techniques for 3-D impedance extraction using mixed boundary element method ” accepted by ASP-DAC’2008

17 Outline Background BEM Solver for Capacitance/ Resistance Extraction Frequency-Dependent Reluctance / Impedance Extraction Substrate Parasitic Extraction Other Works on Interconnect Modeling/ Analysis

18 BEM-based substrate extraction Substrate coupling in mixed-signal IC f< GHz, resistive coupling is primary Higher frequency, both resistive and capacitive (even L) coupling are considered Problem solved with BEM Resistive model: Plate contact, multi-layer substrate, substrate with lateral resistivity variation Analog of capacitance extraction Steady current field Three kinds of boundary Extend to resistive & capacitive model: Introduce complex-valued conductivity

19 BEM-based substrate extraction subDBEM Non-uniform element partition Condense linear system QMM technique Several or tens times faster than Green’s function based method reported in literatures Easily handle non-stratified substrate subRCbem Calculate equivalent Z considering R, C coupling A two-step approach for multiple frequencies For each frequency, only solve a matrix whose order is the number of elements on layer interface Experiments exhibit advantages over ASITIC of UCB

20 Relevant papers Z. Ye, W. Yu, Z. Yu, “Efficient 3D capacitance extraction considering lossy substrate with multi-layered Green’s function,” IEEE Trans. Microwave Theory Tech., May 2006, 54(5): X. Wang, W. Yu, Z. Wang, “Efficient direct boundary element method for resistance extraction of substrate with arbitrary doping profile,” IEEE Trans. Computer-Aided Design, Dec. 2006, 25(12): W. Yu, X. Wang, Z. Ye, Z. Wang, “Efficient extraction of frequency-dependent substrate parasitics using direct boundary element method,” submitted to IEEE Trans. Computer-Aided Design

21 Outline Background BEM Solver for Capacitance/ Resistance Extraction Frequency-Dependent Reluctance / Impedance Extraction Substrate Parasitic Extraction Other Works on Interconnect Modeling/ Analysis

22 Other works on interconnect Capacitance extraction considering process variation Consider window-based chip-level extraction Propose technique for inter-window capacitance covariance induced by spatial correlation Practical for full-chip or full-path variation-aware extraction Transient simulation through frequency domain Solve for frequency-domain response Rational approximation using vector fitting Applied to analysis of P/G grid and clock network Eye-diagram prediction for LTI system Predict the worst-case metrics of signaling quality, like eye- opening voltage, timing jitter, from the system’s step response Used in transmission line design

23 Relevant papers Papers W. Zhang, W. Yu, et. al, “An efficient method for chip-level statistical capacitance extraction considering process variations with spatial correlation,” accepted by DATE’ 2008 L. Zhang, W. Yu, et. al, “Clock skew analysis via vector fitting in frequency domain,” accepted by ISQED’2008 W. Yu, R. Shi, et. al, “Accurate eye-diagram prediction and its application for off-chip signaling schemes,” submitted L. Zhang, W. Yu, et. al, “Low power passive equalizer optimization using tritonic step response,” submitted

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