Maurice Goodrick, Bart Hommels129-10-2007 CALICE DAQ, UCL DIF & intermediate board Intermediate board: Power distribution (& pulsing?!)‏ Clock fanout Level.

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Presentation transcript:

Maurice Goodrick, Bart Hommels CALICE DAQ, UCL DIF & intermediate board Intermediate board: Power distribution (& pulsing?!)‏ Clock fanout Level conversion Sensors for T, V, I, etc. DIF: FPGA, RAM, USB, DIF and LDA links, etc. Powered from I.B. Stand-alone operation

Maurice Goodrick, Bart Hommels CALICE DAQ, UCL DIF stacking Tight space constraints and odd requirements: custom DIF board design 10mm

Maurice Goodrick, Bart Hommels CALICE DAQ, UCL DIF status Keep DIF simple hence predictable (no local ‘memory management’, for example)‏ DIF proto: large Xilinx FPGA, to be slimmed down for final DIF

Maurice Goodrick, Bart Hommels CALICE DAQ, UCL DIF block diagram – 1 level down

Maurice Goodrick, Bart Hommels CALICE DAQ, UCL DIF status Design ‘frozen’ (but not too cold), board layout well under way Firmware: Marc contributed hugely by donating his sync. 8b/10b encoded link VHDL Now the hard work begins!

Maurice Goodrick, Bart Hommels CALICE DAQ, UCL project planning & needs: Revised project planning for 2008 & 2009: DAQtest ‘08: –‘minimal DIF’ hardware & firmware EUDET beam test ‘09: –full-fledged DIF hardware&firmware –Intermediate board for EUDET module slab