TDC status and to do 1. Status of TDC design 2. List of future activities

Status of TDC ● TDC definition (and responsible designers) – HitArbiters (Alex) – DLL (Lukas) ● DLL state machine (Alex) – Fine timestamp registers (Gianluca) ● Fine timestamp encoder (Gianluca) – Edge Detection (Elena) – Interconnecting Bus (Gianluca) – Coarse timestamp register (Gianluca) – Coarse timestamp generator (Gianluca) – Readout control (Alex + Gianluca)

TDC layout 16/02/2011

Status of DLL ● DLL (Lukas) – Schematic + Layout passing DRC, Antenna, LVS checks – Full and very in depth characterization study. Detailed documentation of characterization produced ● Study and approval of the characterization by the team ● State machine (Alex) – To be implemented with minor changes from the prototype chip – Decision on design of control circuitry taken last meeting – Status:

DLL layout 16/02/2011

Status of fine timestamp registers ● Existing 32b registers from Sakari modified – Gianluca. With lot of help from Lukas and Elena – No changes to buffer/FF level cells ● Added parallel outputs to layout ● Tuned layout of power stripes ● Added explicit sub pins (no use of global nets now) ● Added tie downs to pass antenna rules – Schematic and Layout pass DRC, Antenna and LVS (Assura & Calibre)

Fine timestamp register 16/02/2011

Status of timestamp Encoder ● Encoder block (Gianluca) – Synthesized from vhdl with SoCEncounter, estimates of load capacitance included. Exported to virtuoso. – Status of verification – Formal conformity check ok – Test bench tests all expected inputs – Tests passed before and after synthesis ● Block: DoubleHitRegEnc – Block joining two fine hit registers and two encoders ● Serial readout of two chained registers – All checks OK (DRC+Antenna+LVS, Assura+Calibre)

Encoder 16/02/2011

DoubleHitRegEnc 16/02/2011

Status of Edge Detector ● Edge Detector (Elena) – Modification of block from prototype asic ● Now one input only, buffering stages added ● Layout modifications – Some of original buffer cells from Sakari have been modified (more compact layout) – Simulation and characterization done ● Document? ● Approval by the team required ● Block: EdgeDetDoubleHitRegEnc – Joins one Edge Detector and one DoubleHitRegEnc – All checks OK (DRC+Antenna+LVS, Assura+Calibre)

EdgeDetector 16/02/2011

Status of TDC ● TDC cell – DLL + 18 fine timestamp registers + 18 encoders + 9 edge detectors + interconnection bus ● Schematic and layout complete – Coord: Gianluca, much work from Elena and Lukas – All connections between present block are routed – All checks OK (DRC + Antenna + LVS, Assura+Calibre

TDC layout 16/02/2011

TO DO ● Next slides: ● Contribute to planning of activities

TDC power distribution ● Power and current consumption of fine hit registers + encoders (Gianluca) ● Extracts parasitics of TDC after first layout release ● Difficulties with Assura, seems ok with Calibre ● Evaluate current/power consumption with parasitics ● Fine hit register ● 32b/5b encoder ● Decide on power distribution based on power/current simulations ● Implement power connections in TDC (schematic + layout)

Coarse timestamps ● Block diagram design of coarse registers and coarse timestamp generator – Gray encoded coarse counter + 1 toggle bit registered on clk falling edge – 9x2 = 18 coarse code registers for rising (12+1 bits) and falling (4+1 bits) edges ● Study needed from concept to block diagram ● Layout floorplanning Full pixel group ECO block from arbiters to pixel fifo – Estimate of parasitics from floorplan ● Validate concept design and layout floorplan – Approval by entire team

Coarse timestamp generator ● Design coarse timestamp generator (Gray) – RTL of coarse counter (triple module redundancy) ● Different approaches to Gray generation possible. To evaluate area/timing tradeoffs – Set of tests + automated verification testbench – Verify coarse code generator (pass set of tests) ● Synthesize coarse code generator – Post synthesis verification + formal conformity ● P&R, layout ● Power and current consumption ● Creation of abstract

Coarse registers ● Design coarse registers – RTL of coarse register. RTL of registers bank – Set of tests + verification testbench of full bank – Verification + formal conformity ● Synthesize coarse register ● P&R, layout of register ● Creation of abstract of coarse register ● Synthesize bank of registers ● Post synthesis verification ● P&R, layout of coarse registers bank

Pixel readout control logic ● Alex + Gianluca ● Adapt from existing prototype block ● Synthesize – Timing constraints depend on a mixture of synthesized and custom layout blocks ● Pixel FIFO design to be considered ● Define a verification plan

FIFO ● Design a FIFO + controller with parameterized depth and width – Responsibilities to be assigned and/or shared – Use it for pixelGroup fifo, Column Fifo, quarter chip fifo... – TMR for the controller – RTL – Define tests + verification test bench ● Synthesis of pixel FIFO – Verification ● P&R, layout ● Creation of abstract

Assembly of pixel group EOC block ● Use building blocks to assemble full pixel group EOC – SoC Encounter ● P&R (from abstract blocks) ● Verification of full pixel group from arbiter inputs to pixel group fifo – Of course post layout – Alex + Matthew + Gianluca

Further brain stormingquestions ● Should we consider hardware verification of selected blocks? – Using Matthew's Spartan kit – Could run in hardware selected portions ● Pixel block readout ● Configuration circuits ● What about scan chains?