TDA1: Time-encoded Differential Absorption ● TDA1 is a switched-capacitor array (SCA) Wilkinson analog-to-digital (AtoD) converter. It is designed to be.

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Presentation transcript:

TDA1: Time-encoded Differential Absorption ● TDA1 is a switched-capacitor array (SCA) Wilkinson analog-to-digital (AtoD) converter. It is designed to be used to convert a single channel of an analog signal from an multi- pixel photon counter (MPPC) to a digitized waveform at very high-speed. The MPPC will be placed in the path of an X-ray LASER source that is duochromatic (two distinct frequencies of X-ray light are represented) so that, after the X-rays pass through an unknown material, the difference in absorption can be detected by the MPPC and measured by the TDA1. Because no off-the-shelf AtoD converters are available that can do this, TDA1 is an application-specific integrated circuit (ASIC).

TDA1 design issues ● must design storage array so that it fits in 1/n of the size of the die to be submitted this semester (reduces the final- level storage array by factor of n) ● must design it to to use just ~1/n the pins that can fit on a single die of that size (no problem) ● if using 3 stage ring oscillator driven by on-board DACs, can only run VCO at ~7 GHz, not the required 12.5 GHz

3-stage ring oscillator: f vs V

TDA1 block diagram

TDA1 specifications

TDA1 necessary simulations ● signal coupling onto die from stud / wire bonding ● signal coupling into sampling array ● signal coupling from sampling to first-level storage array ● signal coupling from first- to second-level storage array ● signal coupling from second- to third-level storage array if appropriate ● time for each LSB worth of signal to leak away from final-level of storage array ● DAC output swing / ability to drive VCO to desired frequency range ● match DAC LSB step size to acceptable sudden sampling frequency change ● matching of fixed 10ps delay stages to variable VCO frequency (impossible?) ● linearity of Wilkinson ramp / performance of current mirror ● maximum speed of accurate Gray code counter when distributed ● digital design simulation (to ensure useful state machine operation) ● maximum digital output speed over LVDS to an external receiver