April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1

April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Visual Status 2 Rx_mac2buf I2C Fifo 31 TDCs TDC 0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash

April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Done: ◦ LM32 + WB-Crossbar + DPRAM + UART ◦ Soft-PLL FMC layout ◦ WR without PCI-express Currently: ◦ Deterministic PHY ◦ Soft PLL (hardware + software). First goal: lock onto a 125 MHz xtal and phase shift under control of LM32 via UART To do (in order of priority): ◦ Endpoint (= MAC) <= Complex! ◦ Mini-nic <= Complex! ◦ Fabric redirector <= probably less complex ◦ PPS generator <= relatively straightforward ◦ 1-wire, SysCon <= easy? Status Listing 3

April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Kintex-7 Deterministic PHY Test Setup (“Master” loop-backed onto itself) 4 BitSlide “00111” Pll_LockDet RstDone Waiting RxSlide KC705 FMC XM105 Debug Card 2x “constant impedance trombone line” (2x ps) Start Stop

April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Kintex-7 Deterministic PHY Test Setup (“Master” loop-backed onto itself) 5 Start Stop

April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Kintex-7 Deterministic PHY Test Results (“Master” loop-backed onto itself) 6 “Start” triggers osciloscope After “Stop” ns a pulse is generated by the receiver The number of bits (= 0,8 ns) the receiver had to slide before (20 bit) Word alignment was achieved Corrected propagation delay from start to stop (=“stop” + BitSlide*0,8 ns)

April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Xilinx University Donations Xilinx granted us KC705 boards (boards received!) At Nikhef we already bought two KC705 boards so there will be a total of four soon. We could use all four boards…: ◦ 2 boards Peter (Master Slave) deterministic phy testing. ◦ 1 board Mesfin (porting and testing WR Spartan-6 based SPEC onto Kintex-7 based KC705) ◦ 1 board Vincent (software development) 7

April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology More status… Soft PLL FMC card ◦ Eagerly awaiting for Kintex7 PHY tests => Expected April 18 th + 1 Week delay because of a wrong FMC- connector delivered. Porting VHDL code to Kintex ◦ Phy & endpoint ongoing  Kintex7 PHY probably ready (to be tested)  SPEC is based on 8 bit deterministic PHY whereas Kintex7 is a 16 bit PHY => Sort out clock domains ◦ Generic fifo in hold  We can use Coregen fifo for kintex 8

April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology More status… SVN Directory structure svn ◦ Structure put into SVN ◦ Project tags, branches and trunk are added under CLBv2!  9 Use:/CLBv2/fw, /CLBv2/hw, /CLBv2/sw (Firmware Hardware, software) /tools Abandoned (should be cleaned soon!): Firmware Hardware white_rabbit test_designs

April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology More status… SVN 10 CLBv2_Design: to be filled in the future with the integrated design TestDesigns: Play as you like to create test designs For verification of various sub blocks Structure within a design: White Rabbit source files (now relativly linked in the directory structure) BPI_Flash: may contain ready to use FPGA configuration file doc: Documentation ip_cores (like output of the Xilinx Core Generator) ISE (if you want to run the ISE GUI) sim: Simulation environment (including scripts and stimuli) syn: Synthesis + Place&Route (including scripts for XST or Mentor graphics Precision) top: top level VHDL file(s) (more files may exist for system level simulation or various FPGA implementations that are part of the system) modules: lower level vhdl entity descriptions (not shown in this example since the design generated in one file (in top directory)

April 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT system considerations: Talked with Sander Mos and Jan-Willem Schmelling: ◦ Optical Line Terminal:  First 25 REAMs engineering samples are delivered late (X-mas 2013). If we are going to wait for them to define the precise OLT then the CLBv2 will probably be delayed.  Is a piggy back OLT a solution?  Piggy back OLT -> Should this be the final implementation? This avoids a second cycle of “Prototype => Test => Pre-Production series => Test => Production => Test” which can easily take two years! ◦ Detector Control  Could this be the same hardware as the CLB if a couple of extra RS232 connections (other things?) are implemented for this function? ◦ WARNING WARNING WARNING!  Late 2013, beginning 2014 the “node” will be deployed. The infrastructure of the Optical Network will then be fixed! We must have proven that the Shore-Station and CLBv2 can deal with a broadcast as it is foreseen now! Don’t underestimate this! 11