EE3A1 Computer Hardware and Digital Design Lecture 13 Detecting faults in Digital Systems.

Slides:



Advertisements
Similar presentations
V. Vaithianathan, AP/ECE
Advertisements

Introduction to CMOS VLSI Design Lecture 17: Design for Testability David Harris Harvey Mudd College Spring 2004.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 261 Lecture 26 Logic BIST Architectures n Motivation n Built-in Logic Block Observer (BILBO) n Test.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 13/12alt1 Lecture 13 Sequential Circuit ATPG Time-Frame Expansion (Lecture 12alt in the Alternative.
EE466: VLSI Design Lecture 17: Design for Testability
Chapter 7: Testing Of Digital Circuits 1 Testing of Digital Circuits M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi.
Design for Testability
Testing of Logic Circuits. 2 Outline  Testing –Logic Verification –Silicon Debug –Manufacturing Test  Fault Models  Observability and Controllability.
16/07/2015CSE1303 Part B lecture notes 1 Hardware Implementation Lecture B17 Lecture notes section B17.
EE 447/EE547 1 VLSI DESIGN Lecture 10 Design for Testability.
Introduction to CMOS VLSI Design Test. CMOS VLSI DesignTestSlide 2 Outline  Testing –Logic Verification –Silicon Debug –Manufacturing Test  Fault Models.
MICROPROCESSOR INPUT/OUTPUT
Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Topics n Sequential machine (§5.2, §5.3) n FSM construction.
CSE477 L28 DFT.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 28: Design for Test Mary Jane Irwin ( )
Design for Testability By Dr. Amin Danial Asham. References An Introduction to Logic Circuit Testing.
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS
EE3A1 Computer Hardware and Digital Design Lecture 6 supplement Common misunderstandings about VHDL processes.
1 Lecture 6 BOOLEAN ALGEBRA and GATES Building a 32 bit processor PH 3: B.1-B.5.
Copyright 2001, Agrawal & BushnellLecture 6: Sequential ATPG1 VLSI Testing Lecture 6: Sequential ATPG n Problem of sequential circuit ATPG n Time-frame.
An introduction to Fault Detection in Logic Circuits By Dr. Amin Danial Asham.
CS/EE 3700 : Fundamentals of Digital System Design
EE3A1 Computer Hardware and Digital Design Worked Examples 3 Test and testability (1)
Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals.
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Functional testing.
Lecture 5: Design for Testability. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 12: Design for Testability2 Outline  Testing –Logic Verification –Silicon.
1 VLSI Design Lecture Four Design & Testing Issues Dr. Richard Spillman PLU Spring 2003.
EGR 2131 Unit 4 Combinational Circuits: Analysis & Design
REGISTER TRANSFER LANGUAGE (RTL)
Topics SRAM-based FPGA fabrics: Xilinx. Altera..
Combinational circuits
DIGITAL LOGIC CIRCUITS
VLSI Testing Lecture 14: System Diagnosis
Hardware Testing and Designing for Testability
VLSI Testing Lecture 6: Fault Simulation
DIGITAL LOGIC CIRCUITS
Algorithms and representations Structural vs. functional test
CPE/EE 428/528 VLSI Design II – Intro to Testing (Part 2)
CPE/EE 428/528 VLSI Design II – Intro to Testing (Part 3)
ECE 434 Advanced Digital System L18
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES
Reading: Hambley Chapters
Lecture 12: Design for Testability
VLSI Testing Lecture 7: Combinational ATPG
Lecture 10 Sequential Circuit ATPG Time-Frame Expansion
Basics Combinational Circuits Sequential Circuits
Basics Combinational Circuits Sequential Circuits Ahmad Jawdat
Chapter 4 Gates and Circuits.
Boolean Algebra and Digital Logic
Fundamentals of Computer Science Part i2
CS/COE0447 Computer Organization & Assembly Language
Lecture 12: Design for Testability
Design for Testability
Lecture 12: Design for Testability
VLSI Testing Lecture 8: Sequential ATPG
CPE/EE 422/522 Advanced Logic Design L17
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Logic Gates.
Fault Models, Fault Simulation and Test Generation
VLSI Testing Lecture 7: Combinational ATPG
Guest Lecture by David Johnston
Topics Switch networks. Combinational testing..
ECE 352 Digital System Fundamentals
ECE 352 Digital System Fundamentals
Lecture 26 Logic BIST Architectures
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Sequential Circuit Analysis
Digital Circuits and Logic
EGR 2131 Unit 12 Synchronous Sequential Circuits
Digital Logic Design Basics Combinational Circuits Sequential Circuits.
Test Data Compression for Scan-Based Testing
Presentation transcript:

EE3A1 Computer Hardware and Digital Design Lecture 13 Detecting faults in Digital Systems

Introduction  From concept to saleable product: 1. Get the specification right 2. Translate to a manufacturable design 3. Check design fulfils the specification 4. Manufacture the design 5. Check that manufactured units are fault-free  For complex systems, step 5 can be very difficult, unless u The designer builds special features into the design that make the circuit easy to test u Design for testability

Basic testing procedure  Initialise the circuit into a known state  Apply the test inputs  Compare outputs with expectation

Example  Simple example circuit ABCE

 One of the units has a fault  Node D has been short-circuited to a voltage supply rail  This node’s value is stuck at logic 0 Example 0 1 ABCE

 We cannot directly probe the node (it is inside the chip)  How do we detect this?  One of the units has a fault  Node D has been short-circuited to a voltage supply rail  This node’s value is stuck at logic 0 Example 0 1 ABCEFaulty E

 Apply all possible combinations of A, B, C  These inputs are called test vectors  Compare output of unit-under-test with expectation  If we find a difference, then the unit is faulty  This circuit requires 8 test vectors  (Truth table has 2 3 =8 rows) Exhaustive Testing 0 1 ABCEFaulty E

Exhaustive test of combinational logic  Generalisation:  n-input combinational system requires 2 n test vectors  Example: system with 32 inputs. u Needs 2 32 = 4  10 9 test inputs. u Using a standard 100 MHz tester would take almost a minute for just one unit u May not be acceptable if we have a high throughput manufacturing line n

Exhaustive test of sequential logic  If system contains state memory, things get much worse.  The sequence in which we apply the inputs becomes significant.  System with n inputs and m state flip flops  2 n distinct inputs  2 m distinct sequences that we can apply these inputs in  Needs 2 n+m test vectors for exhaustive test. n

Exhaustive test of sequential logic  Example: system with 32 inputs, containing 32 state bits  Need = 2 64 = 2x10 19 test vectors  100 MHz tester requires 6,000 years for one unit

Non-Exhaustive Testing 0 1 ABCEFaulty E  We cannot afford to apply every possible test input  Instead we must select a few  Suppose we can use only two test inputs  Will we detect the fault?

Non-Exhaustive Testing 0 1 ABCEFaulty E  We cannot afford to apply every possible test input  Instead we must select a few  Suppose we can use only two test inputs.  Will we detect the fault? This is OKOutput of faulty unit is not identical to output of good unit: Fault is detected

Non-Exhaustive Testing 0 1 ABCEFaulty E  We cannot afford to apply every possible test input  Instead we must select a few  Suppose we can use only two test inputs.  Will we detect the fault?  OK if we choose a set that includes ABC=111  Otherwise fault is not detected This is no goodOutput of faulty unit is identical to output of good unit: Fault is missed

Non-Exhaustive Test  If we can’t use all possible test vectors, we may miss faults  The percentage of faults that is detected by a set of test vectors is the fault coverage  If we can’t use all possible test vectors, fault coverage may be less than 100%.  Some choices of test vectors will have high fault coverage  Other choices will have low fault coverage  How do we choose test vectors that maximise fault coverage? (Ideally to 100%)

Fault modelling  Need some idea of the failure modes of our system (i.e. what a fault looks like)  Then we can do some detective work, and check whether any of these failure modes is present  The fault with our system was a stuck-at-one ( s-a-0 ) fault.  Very common.  Node is shorted to high voltage rail, is also common.  stuck-at-one ( s-a-1 ) fault.  Simple test procedures assume only s-a-0 and s-a-1 faults can occur, and check each node for these faults

Path sensitisation methods  For each node in the circuit (A,B,C,D,E) u For each possible fault (s-a-0, s-a-1) u Find a set of inputs that will u test that node for the fault u steer the result of the test to an output

Path sensitisation methods  For each node in the circuit (A,B,C,D,E) u For each possible fault (s-a-0, s-a-1) u Find a set of inputs that will u test that node for the fault u steer the result of the test to an output Is D s-a-0? 1 1 Get result of test to output Set inputs to try to drive this node to 1 1 if good 0 if faulty

Sensitivity  We need to get the result of the test at D to the output E  If we choose C=0 u Then E=0 regardless of the value at D u E is insensitive to D  No good: can’t distinguish between faulty and good system Is D s-a-0? 1 1 Set inputs to try to drive this node to 1 1 if good 0 if faulty 0 0 Get result of test to output

Sensitivity  We need to get the result of the test at D to the output E  If we choose C=1 u Then E=1 if the circuit is good and 0 otherwise u E is sensitive to D  We can tell whether or not the circuit has this fault Is D s-a-0? 1 1 Set inputs to try to drive this node to 1 1 if good 0 if faulty Get result of test to output 1

Path sensitisation methods Is D s-a-0? if good 0 if faulty 1 FaultInputs: ABCFault free EFaulty E D s-a  For each node in the circuit (A,B,C,D,E) u For each possible fault (s-a-0, s-a-1)

Path sensitisation methods  For each node in the circuit (A,B,C,D,E) u For each possible fault (s-a-0, s-a-1) Is D s-a-1? Make E senstitive to D Set inputs to try to drive this node to 0 0 if good 1 if faulty or 1 FaultInputs: ABCFault free EFaulty E D s-a D s-a-1001 or 011 or 10101

Path sensitisation methods  For each node in the circuit (A,B,C,D,E) u For each possible fault (s-a-0, s-a-1) Is E s-a-0? Set inputs to try to drive this node to 1 1 if good 0 if faulty FaultInputs: ABCFault free EFaulty E D s-a E s-a D s-a-1001 or 011 or

Path sensitisation methods FaultInputs: ABCFault free EFaulty E A s-a B s-a C s-a D s-a-1001,101,01101 E s-a-1000,001,010,100,101,110,01101 A s-a B s-a C s-a D s-a E s-a  And so on…

Path sensitisation methods FaultInputs: ABCFault free EFaulty E A s-a B s-a C s-a D s-a-1001,101,01101 E s-a-1000,001,010,100,101,110,01101 A s-a B s-a C s-a D s-a E s-a  Find a set of test vectors that covers all possible faults  ABC = 111

Path sensitisation methods FaultInputs: ABCFault free EFaulty E A s-a B s-a C s-a D s-a-1001,101,01101 E s-a-1000,001,010,100,101,110,01101 A s-a B s-a C s-a D s-a E s-a  Find a set of test vectors that covers all possible faults  ABC = 111, 011

Path sensitisation methods FaultInputs: ABCFault free EFaulty E A s-a B s-a C s-a D s-a-1001,101,01101 E s-a-1000,001,010,100,101,110,01101 A s-a B s-a C s-a D s-a E s-a  Find a set of test vectors that covers all possible faults  ABC = 111, 011, 101

Path sensitisation methods FaultInputs: ABCFault free EFaulty E A s-a B s-a C s-a D s-a-1001,101,01101 E s-a-1000,001,010,100,101,110,01101 A s-a B s-a C s-a D s-a E s-a  Find a set of test vectors that covers all possible faults  ABC = 111, 011, 101, 110

Evaluation  Path sensitisation method u ABC = 111, 011, 101, 110 u 4 test vectors  Exhaustive test u ABC = 000, 001, 010, 011, 100, 101, 110, 111 u 8 test vectors

Generalisation  Exhaustive test u 2 number-of-inputs test vectors  Path sensitisation method u 2 x number-of-nodes

Generalisation  Example circuit u 32-bit combinational multiplier circuit u Number of inputs = 64 u Number of nodes = 7,200  Path-Sensitisation requires 2 x 7200 = 14,400 test vectors  On 100 MHz tester, takes 144  s u Batch of 10,000 chips tested in 14.4 seconds  Exhaustive test requires 2 64 = 1.8 x test vectors u On 100 MHz tester, takes 6,000 years u Batch of 10,000 chips tested in 60 million years

More about Sensitivity  Test for A s-a-0: u Drive A with 1 u Make E sensitive to A Is A s-a-0? 1 1 if good 0 if faulty

More about Sensitivity  Test for A s-a-0: u Drive A with 1 u Make E sensitive to A  What should B be? Is A s-a-0? if good 0 if faulty 0 Test result is lost: no good 0

More about Sensitivity  Test for A s-a-0: u Drive A with 1 u Make E sensitive to A  B must be 1  What about C? Is A s-a-0? if good 0 if faulty 0 0 Test result is lost: no good

More about Sensitivity  Test for A s-a-0: u Drive A with 1 u Make E sensitive to A  B must be 1  C must be 1 Is A s-a-0? if good 0 if faulty 1

More about Sensitivity  Test for A s-a-0: u Drive A with 1 u Make E sensitive to A  Intuitively BC=11  How do we handle more complicated cases, where answer is not obvious? Is A s-a-0? if good 0 if faulty 1

Derivative  Derivative is rate of change  Rate of change of distance x with respect to time t x t is bigis smallis zero  If derivative is zero, x is insensitive to t  If non-zero, then x is sensitive to t

 We want to know if E is sensitive to A  Boolean difference of E with respect to A is  Digital equivalent of derivative  If then E is sensitive to A  If then E is not sensitive to A Boolean Difference

Computation of Boolean Difference  Boolean relation between E and A is E=A.B.C  Work out value of this function with A set to 1  Work out value of this function with A set to 0  XOR the two together  This is the Boolean difference

 Boolean relation between E and A is E=A.B.C  Work out value of this function with A set to 1  Work out value of this function with A set to 0  XOR the two together  This is the Boolean difference  (1.B.C)  (0.B.C)  = B.C  0  = B.C.0 + B.C.0  = 0 + B.C.1  = B.C Computation of Boolean Difference Using identity X  Y=X.Y+X.Y

 Boolean relation between f and x i is  Work out value of this function with x i set to 1  Work out value of this function with x i set to 0  XOR the two together  This is the Boolean difference Computation of Boolean Difference x 1 x 2 x 3 x n z

Using Boolean Differences  Test for A s-a-0: u Drive A with 1 u Make E sensitive to A, i.e. make  But  So we need to make B=1 and C=1 Is A s-a-0? if good 0 if faulty

Enhancing Testability  Deeply embedded nodes are hard to test  Finding input values that will drive test onto NUT is hard u Too many logic gates between inputs and NUT  Sensitizing an output to the fault is also hard u Too many logic gates between NUT and outputs  We’d like to ensure that nodes do not have a large logic depth from the inputs or outputs InputsOutputs Node-Under-Test

System Partitioning  Most systems can be partitioned into sub-systems InputsOutputs Node-Under-Test

System Partitioning  Most systems can be partitioned into sub-systems Inputs Outputs S1 S3 S2 Node-Under-Test If we can gain direct access to these lines, then testing is much easier

Test Access Ports  Can we just copy the intermediate data to output pins? S1S2 Inputs Outputs S3  Adds many extra pins to chip  Makes chip very expensive Test Data Out 1 TDO2

Test Access Ports  Do parallel-to-serial conversion before copy-out S1S2 Inputs Outputs S3 Test Data Out 1 TDO2  Test Data Outputs are now only 1 bit wide  Doesn’t add much cost to chip  (But takes many clock cycles to shift data out)

Test Access Ports S1S2 Inputs Outputs S3 Test Data Out 1 TDO2  Add a way to get the test data in  Data is shifted in serially then converted to parallel  MUX controls whether S2 takes inputs from S1 or from TDI1 Test Data In 1TDI2

Test Access Ports S1S2 Inputs Outputs S3 Test Data Out 1 TDO2  Add a pin that controls whether the chip is in test mode or normal mode  In normal mode, the chip ignores the Test Access Ports  In test mode each stage receives input from TDI and sends output to TDO  Each node is now much easier to test Test Data In 1TDI2Normal/test

Summary  Efficient testing methods are based on u deciding what faults are possible and u testing circuit to see if any of the faults are present  Testability of design can be enhanced by incorporating special features at design stage

Questions  Find a test vector that will test for the fault D s-a-1.  Choose from ABC = (a) 000 (b) 001 (c) 010 (d) 011 (e) 100

Questions  What is the value of  (i.e. under what condition will a change in A cause a change in C) (a) a+b (b) 1 (c) a (d) b (e) b