A Low Supply Voltage CMOS Bandgap And Sub-threshold Voltage Reference Anurag Sindhu(Y5106) Ashish Bhatia (Y5121) EE610 Course Project

Basic Idea For generating a temperature independent voltage reference, we need –Voltage with negative TC (Temp Coeff.) : V 1 –Voltage with positive TC : V 2 –A circuit to linearly combine them(a 1 V 1 + a 2 V 2 ) such that net voltage has (almost) zero TC δ(a 1 V 1 + a 2 V 2) / δT = 0

Negative TC Voltage V BE of BJT decreases with temperature

Positive TC Voltage V BE1 – V BE2 = V T ln(J c1 /J c2 ) = V PTAT increases with temp if J c1 > J c2 In our case J c1 /J c2 = (Ic 1 *A 2 )/(Ic 2 *A 1 ) = 10*10 = 100 => V BE1 – V BE2 = 120 mV (approx) at 300K

Voltage to Current Conversion I = k(V BE1 -(V BE2 -V THP2 )-V THP1 ) 2 = k(V BE1 -V BE2 ) 2 …(1)

Current to Voltage Conversion (with Amplification) 5I = 0.2k(V BG -(V BE2 -V THP2 )-V THP6 ) 2 = 0.2k(V BG -V BE2 ) 2 …(2)

I = k(V BE1 -V BE2 ) 2 …(1) 5I = 0.2k(V BG -V BE2 ) 2 …(2) Solving (1) and (2) V BG = V BE2 + 5(V BE1 -V BE2 )

I = k(V BE1 -V BE2 ) 2 …(1) 5I = 0.2k(V BG -V BE2 ) 2 …(2) Solving (1) and (2) V BG = V BE2 + 5(V BE1 -V BE2 ) increases with Temp 0.4 mV/K decreases with Temp 2mV/K

IIIII5I11 I10 I2I5I10 I M1M1 M6M6 M5M5 Q1Q1 M3M3 M4M4 M8M8 M9M9 M 10 M 11 M 12 McMc M2M2 M7M7 Q2Q2 I

Our Innovation To generate dual voltage references –Bandgap reference (1.157 V) –Sub-threshold reference (326 mV)

Circuit for sub-threshold reference M 13 and M 14 acts as Voltage Divider to produce sub threshold output = 326 mV

Complete Circuit

Simulation Results

Vmax = V Vmin = 1.140V Variation = 18 mV (from -25C to 75C)

Vmax = mV Vmin = mV Variation = 12 mV (from -25C to 75C)

Vmax = mV Vmin = mV Variation = 20 mV (V dd varying from 1.3 to 1.5V)

Vmax = 308 mV Vmin = 292 mV Variation = 16 mV (V dd varying from 1.3 to 1.5V)

Advantages Does not use Resistance or Op Amp => can be fabricated on any Digital CMOS technology Dual Voltage reference available => can be used in low power systems –Devices operate at sub-threshold voltage during low computation periods –Jump to saturation mode during high computation periods

Main Challenge Short Channel Transistors do not follow square law characteristics => adjustment to ideal W/L values, through iteration for getting desired current

References “A Low-Supply-Voltage CMOS Sub-Bandgap Reference”, Adriana Becker-Gomez, T. Lakshmi Viswanathan, T. R. Viswanathan, IEEE Transactions On Circuits And Systems—II: Express Briefs, Vol. 55, No. 7, July 2008 “Design of Analog CMOS Integrated Circuits”, Behzad Razavi, Tata McGraw Hill Publishers (Edition 2002)