A. Salamon - TDAQ WG Pisa 27/03/ Lkr/L0 Trigger V. Bonaiuto, N. De Simone, L. Federici, A. Fucci, G. Paoluzzi, A. Salamon, G. Salina, E. Santovetti, F. Sargeni, S. Venditti

Oxford - TWEPP /09/ The liquid krypton calorimeter L0 trigger Pixel based trigger processor with 4x4 calorimeter cell tiles Identifies electromagnetic clusters in the calorimeter and prepares a time-ordered list of reconstructed clusters (time, position and energy) for the L0 Trigger Processor Low granularity readout independent from CREAM full granularity readout Fast readout for L1 software triggers and/or Region of Interest for the Lkr full granularity readout at L1 Inst. hit rate: 30 MHz Time resolution: ~1.5 ns Latency < 100 us

Oxford - TWEPP /09/ Lkr L0 trigger implementation 28 x 7 x 1 x 36 9U TEL62 electronics modules dedicated mezzanines 3 9U crates 864 input channels (tiles), MHz per tile from the calorimeter readout modules (CREAM) over cat 5 Ethernet cables 1 trigger output channel (Gbit Ethernet) to the L0 Trigger Processor 28 raw data + 7 reconstructed clusters readout channels to L1 and DAQ Less than 100 m s output latency 28 x

A. Salamon - TDAQ WG Pisa 27/03/ Readout and data rate (S. Venditti) 32 channels (Lkr trigger tiles) for each TEL62 -> 8 Lkr trigger tiles for each PP Each channel receives one 16 bit word every 25 ns Not zero suppressed readout -> data rate independent from hit rate S. Venditti wrote an interface to adapt our data format to the TDC data format DDR write: lossless zero suppression before writing in the DDR -> 40 MHz x 8 bit for each PP/DDR (continous data stream, 8 bit every 25 ns) DDR read: 1 MHz x 5 samples x 8 bit for each PP/DDR (8 bit x 5 samples every L0_yes) From the readout point of view Lkr/L0 is like a TDC

A. Salamon - TDAQ WG Pisa 27/03/ L0 trigger and processing (V. Bonaiuto, L. Federici, F. Sargeni) Preliminary firmware, currently being developed, we can only give some estimate Nios II processing Pulse reconstruction in 70 clock cycles (there are 2 divisions, each one 30 clock cycles) Time to process one peak -> 70 clock cycles / 160 MHz = 440 ns (Over)estimated hit rate per PP is 5 MHz -> 200 ns 2-3 Nios II processor per PP LE (Logic Elements) and memory requirements per PP Firmware still under development, we have some estimates (for Cyclone II) 3 Nios II processors -> 20 kLEs, 220 kbit

A. Salamon - TDAQ WG Pisa 27/03/ Common firmware, TEL62 tests, TEL62 repair and crates We plan to use as much as possible of existing TDC firmware and software Not possible to give help on common firmware and software development (man power) TEL62 JTAG test developed (see report from N. De Simone) Any other contribution on TEL62 production and tests to be discussed Some Stratix III bought at the end of > now at CERN TEL62: bought 3 TEL62 1 (# 9) in our lab and we will take care of repair 2 to be repaired by Pisa FPGA size? Crates: 1 crate bought 2/3 to be bought Gianluca reported some malfunctioning. Any news concerning repair/replacement?

A. Salamon - TDAQ WG Pisa 27/03/ Common tests requirements 2 weeks in July: stand-alone tests without CREAM 2 weeks between October and December: integration tests with CREAM