Data Hazards Dependent instructions add %g1, %g2, %g3 sub %l1, %g3, %o0 Forwarding helps, but not all hazards can be avoided

Data Hazard Classification Three types of hazard: –RAW (Read After Write) MIPS register access –WAW (Write After Write) Writes in more than one stage –WAR (Write After Read) Early writes and late reads –RAR (Read After Read) not a hazard

Control Hazards Branches cause a one cycle stall!  –Performance impact of 10%–30%

Reducing Branch Penalty Four simple static schemes: –Freeze pipeline (simple) –Assume not-taken Cannot allow state changes until outcome is known –Assume taken Only useful if destination address is known early –Delayed branch Introduce branch-delay slot(s)

Filling the Delay Slots Compiler must try to find useful work for the delay slot from: –Before the branch Always useful –From target May increase code size –From fall-through Must be very careful

Filling Delay Slots Usually also have a cancelling or nullifying branch –SPARC: annulled branch –Allows more freedom in filling slot

A.3. Implementation of Pipelining Details the implementation of MIPS pipeline

Implementing Control Moving an instruction from ID to EX is called instruction issue MIPS can detect all data hazards in ID and stall before issue Hardware (comparators) detects hazard and inserts a no-op Similarly for forwarding

Minimising Control Hazards Need to test registers and calculate address early MIPS: can do both in ID –Requires Zero test/compare hardware Adder to calculate destination address –One cycle stall Plus one-cycle data hazard stall if register is set by preceding instruction Other architectures: even worse (4-7 cycles)

Problems! Some further complications… –Exceptions (or interrupts, faults, traps, etc.) –Instruction set issues

Dealing with Exceptions Any instruction in the pipeline may cause an exception Different types of exception –Synchronous/asynchronous –User requested/coerced –User maskable/nonmaskable –Within/between instructions –Resumable/terminating Difficult case is synchronous, coerced, resumable exceptions within instructions

Handling Exceptions Pipeline must be shut down and state saved for restart –Force trap into pipeline on next IF –Turn off all writes by current and subsequent instructions –Save PC of exception-generating instruction (plus further PCs for delay slots)

Handling Exceptions Precise Exceptions –Instructions before interrupting instruction are completed –Instructions after the interrupting instruction can be restarted from scratch Difficult for FP Necessary for VM!

MIPS Exception Handling May occur in almost all stages: –IF: page fault, alignment, memory protection –ID: undefined or illegal instruction –EX: arithmetic –MEM: page fault, alignment, protection –WB: none Exceptions may occur simultaneously, or even “out of order”

MIPS Exception Handling To handle in order: –Exception is noted and carried along with instruction through the pipeline –All writes/state-changes are turned off –Exceptions resolved at MEM  WB transition

Instruction Set Issues MIPS easy –Instructions are only committed at MEM  WB transition Other architectures are more difficult –Instructions may update state early –FP more difficult –Memory updating ops (e.g. string moves)